1//===-- RISCV.td - Describe the RISC-V Target Machine ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// RISC-V subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15include "RISCVFeatures.td" 16 17//===----------------------------------------------------------------------===// 18// Named operands for CSR instructions. 19//===----------------------------------------------------------------------===// 20 21include "RISCVSystemOperands.td" 22 23//===----------------------------------------------------------------------===// 24// Registers, calling conventions, instruction descriptions. 25//===----------------------------------------------------------------------===// 26 27include "RISCVSchedule.td" 28include "RISCVRegisterInfo.td" 29include "RISCVCallingConv.td" 30include "RISCVInstrInfo.td" 31include "GISel/RISCVRegisterBanks.td" 32 33//===----------------------------------------------------------------------===// 34// RISC-V macro fusions. 35//===----------------------------------------------------------------------===// 36 37include "RISCVMacroFusion.td" 38 39//===----------------------------------------------------------------------===// 40// RISC-V Scheduling Models 41//===----------------------------------------------------------------------===// 42 43include "RISCVSchedRocket.td" 44include "RISCVSchedSiFive7.td" 45include "RISCVSchedSiFiveP400.td" 46include "RISCVSchedSyntacoreSCR1.td" 47 48//===----------------------------------------------------------------------===// 49// RISC-V processors supported. 50//===----------------------------------------------------------------------===// 51 52include "RISCVProcessors.td" 53 54//===----------------------------------------------------------------------===// 55// Define the RISC-V target. 56//===----------------------------------------------------------------------===// 57 58def RISCVInstrInfo : InstrInfo { 59 let guessInstructionProperties = 0; 60} 61 62def RISCVAsmParser : AsmParser { 63 let ShouldEmitMatchRegisterAltName = 1; 64 let AllowDuplicateRegisterNames = 1; 65} 66 67def RISCVAsmWriter : AsmWriter { 68 int PassSubtarget = 1; 69} 70 71def RISCV : Target { 72 let InstructionSet = RISCVInstrInfo; 73 let AssemblyParsers = [RISCVAsmParser]; 74 let AssemblyWriters = [RISCVAsmWriter]; 75 let AllowRegisterRenaming = 1; 76} 77