1//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// RISC-V subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15def FeatureStdExtM 16 : SubtargetFeature<"m", "HasStdExtM", "true", 17 "'M' (Integer Multiplication and Division)">; 18def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, 19 AssemblerPredicate<(all_of FeatureStdExtM), 20 "'M' (Integer Multiplication and Division)">; 21 22def FeatureStdExtA 23 : SubtargetFeature<"a", "HasStdExtA", "true", 24 "'A' (Atomic Instructions)">; 25def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, 26 AssemblerPredicate<(all_of FeatureStdExtA), 27 "'A' (Atomic Instructions)">; 28 29def FeatureStdExtF 30 : SubtargetFeature<"f", "HasStdExtF", "true", 31 "'F' (Single-Precision Floating-Point)">; 32def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, 33 AssemblerPredicate<(all_of FeatureStdExtF), 34 "'F' (Single-Precision Floating-Point)">; 35 36def FeatureStdExtD 37 : SubtargetFeature<"d", "HasStdExtD", "true", 38 "'D' (Double-Precision Floating-Point)", 39 [FeatureStdExtF]>; 40def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, 41 AssemblerPredicate<(all_of FeatureStdExtD), 42 "'D' (Double-Precision Floating-Point)">; 43 44def FeatureExtZfh 45 : SubtargetFeature<"experimental-zfh", "HasStdExtZfh", "true", 46 "'Zfh' (Half-Precision Floating-Point)", 47 [FeatureStdExtF]>; 48def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">, 49 AssemblerPredicate<(all_of FeatureExtZfh), 50 "'Zfh' (Half-Precision Floating-Point)">; 51 52def FeatureStdExtC 53 : SubtargetFeature<"c", "HasStdExtC", "true", 54 "'C' (Compressed Instructions)">; 55def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, 56 AssemblerPredicate<(all_of FeatureStdExtC), 57 "'C' (Compressed Instructions)">; 58 59def FeatureExtZba 60 : SubtargetFeature<"experimental-zba", "HasStdExtZba", "true", 61 "'Zba' (Address calculation 'B' Instructions)">; 62def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">, 63 AssemblerPredicate<(all_of FeatureExtZba), 64 "'Zba' (Address calculation 'B' Instructions)">; 65def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">; 66 67def FeatureExtZbb 68 : SubtargetFeature<"experimental-zbb", "HasStdExtZbb", "true", 69 "'Zbb' (Base 'B' Instructions)">; 70def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, 71 AssemblerPredicate<(all_of FeatureExtZbb), 72 "'Zbb' (Base 'B' Instructions)">; 73 74def FeatureExtZbc 75 : SubtargetFeature<"experimental-zbc", "HasStdExtZbc", "true", 76 "'Zbc' (Carry-Less 'B' Instructions)">; 77def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, 78 AssemblerPredicate<(all_of FeatureExtZbc), 79 "'Zbc' (Carry-Less 'B' Instructions)">; 80 81def FeatureExtZbe 82 : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true", 83 "'Zbe' (Extract-Deposit 'B' Instructions)">; 84def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">, 85 AssemblerPredicate<(all_of FeatureExtZbe), 86 "'Zbe' (Extract-Deposit 'B' Instructions)">; 87 88def FeatureExtZbf 89 : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true", 90 "'Zbf' (Bit-Field 'B' Instructions)">; 91def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">, 92 AssemblerPredicate<(all_of FeatureExtZbf), 93 "'Zbf' (Bit-Field 'B' Instructions)">; 94 95def FeatureExtZbm 96 : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true", 97 "'Zbm' (Matrix 'B' Instructions)">; 98def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">, 99 AssemblerPredicate<(all_of FeatureExtZbm), 100 "'Zbm' (Matrix 'B' Instructions)">; 101 102def FeatureExtZbp 103 : SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true", 104 "'Zbp' (Permutation 'B' Instructions)">; 105def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">, 106 AssemblerPredicate<(all_of FeatureExtZbp), 107 "'Zbp' (Permutation 'B' Instructions)">; 108 109def FeatureExtZbr 110 : SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true", 111 "'Zbr' (Polynomial Reduction 'B' Instructions)">; 112def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">, 113 AssemblerPredicate<(all_of FeatureExtZbr), 114 "'Zbr' (Polynomial Reduction 'B' Instructions)">; 115 116def FeatureExtZbs 117 : SubtargetFeature<"experimental-zbs", "HasStdExtZbs", "true", 118 "'Zbs' (Single-Bit 'B' Instructions)">; 119def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, 120 AssemblerPredicate<(all_of FeatureExtZbs), 121 "'Zbs' (Single-Bit 'B' Instructions)">; 122 123def FeatureExtZbt 124 : SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true", 125 "'Zbt' (Ternary 'B' Instructions)">; 126def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">, 127 AssemblerPredicate<(all_of FeatureExtZbt), 128 "'Zbt' (Ternary 'B' Instructions)">; 129 130// Some instructions belong to both the basic and the permutation 131// subextensions. They should be enabled if either has been specified. 132def HasStdExtZbbOrZbp 133 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">, 134 AssemblerPredicate<(any_of FeatureExtZbb, FeatureExtZbp), 135 "'Zbb' (Base 'B' Instructions) or " 136 "'Zbp' (Permutation 'B' Instructions)">; 137 138def FeatureExtZbproposedc 139 : SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc", "true", 140 "'Zbproposedc' (Proposed Compressed 'B' Instructions)">; 141def HasStdExtZbproposedc : Predicate<"Subtarget->hasStdExtZbproposedc()">, 142 AssemblerPredicate<(all_of FeatureExtZbproposedc), 143 "'Zbproposedc' (Proposed Compressed 'B' Instructions)">; 144 145def FeatureStdExtB 146 : SubtargetFeature<"experimental-b", "HasStdExtB", "true", 147 "'B' (Bit Manipulation Instructions)", 148 [FeatureExtZba, 149 FeatureExtZbb, 150 FeatureExtZbc, 151 FeatureExtZbe, 152 FeatureExtZbf, 153 FeatureExtZbm, 154 FeatureExtZbp, 155 FeatureExtZbr, 156 FeatureExtZbs, 157 FeatureExtZbt]>; 158def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">, 159 AssemblerPredicate<(all_of FeatureStdExtB), 160 "'B' (Bit Manipulation Instructions)">; 161 162def FeatureNoRVCHints 163 : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", 164 "Disable RVC Hint Instructions.">; 165def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, 166 AssemblerPredicate<(all_of(not FeatureNoRVCHints)), 167 "RVC Hint Instructions">; 168 169def FeatureStdExtV 170 : SubtargetFeature<"experimental-v", "HasStdExtV", "true", 171 "'V' (Vector Instructions)">; 172def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">, 173 AssemblerPredicate<(all_of FeatureStdExtV), 174 "'V' (Vector Instructions)">; 175 176def FeatureStdExtZvlsseg 177 : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true", 178 "'Zvlsseg' (Vector segment load/store instructions)", 179 [FeatureStdExtV]>; 180def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">, 181 AssemblerPredicate<(all_of FeatureStdExtZvlsseg), 182 "'Zvlsseg' (Vector segment load/store instructions)">; 183 184def FeatureExtZvamo 185 : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true", 186 "'Zvamo' (Vector AMO Operations)", 187 [FeatureStdExtV]>; 188def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">, 189 AssemblerPredicate<(all_of FeatureExtZvamo), 190 "'Zvamo' (Vector AMO Operations)">; 191 192def Feature64Bit 193 : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; 194def IsRV64 : Predicate<"Subtarget->is64Bit()">, 195 AssemblerPredicate<(all_of Feature64Bit), 196 "RV64I Base Instruction Set">; 197def IsRV32 : Predicate<"!Subtarget->is64Bit()">, 198 AssemblerPredicate<(all_of (not Feature64Bit)), 199 "RV32I Base Instruction Set">; 200 201defvar RV32 = DefaultMode; 202def RV64 : HwMode<"+64bit">; 203 204def FeatureRV32E 205 : SubtargetFeature<"e", "IsRV32E", "true", 206 "Implements RV32E (provides 16 rather than 32 GPRs)">; 207def IsRV32E : Predicate<"Subtarget->isRV32E()">, 208 AssemblerPredicate<(all_of FeatureRV32E)>; 209 210def FeatureRelax 211 : SubtargetFeature<"relax", "EnableLinkerRelax", "true", 212 "Enable Linker relaxation.">; 213 214foreach i = {1-31} in 215 def FeatureReserveX#i : 216 SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", 217 "true", "Reserve X"#i>; 218 219def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore", 220 "true", "Enable save/restore.">; 221 222//===----------------------------------------------------------------------===// 223// Named operands for CSR instructions. 224//===----------------------------------------------------------------------===// 225 226include "RISCVSystemOperands.td" 227 228//===----------------------------------------------------------------------===// 229// Registers, calling conventions, instruction descriptions. 230//===----------------------------------------------------------------------===// 231 232include "RISCVSchedule.td" 233include "RISCVRegisterInfo.td" 234include "RISCVCallingConv.td" 235include "RISCVInstrInfo.td" 236include "RISCVRegisterBanks.td" 237include "RISCVSchedRocket.td" 238include "RISCVSchedSiFive7.td" 239 240//===----------------------------------------------------------------------===// 241// RISC-V processors supported. 242//===----------------------------------------------------------------------===// 243 244def : ProcessorModel<"generic-rv32", NoSchedModel, []>; 245def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; 246 247def : ProcessorModel<"rocket-rv32", RocketModel, []>; 248def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>; 249 250def : ProcessorModel<"sifive-7-rv32", SiFive7Model, []>; 251def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit]>; 252 253def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM, 254 FeatureStdExtA, 255 FeatureStdExtC]>; 256 257def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit, 258 FeatureStdExtM, 259 FeatureStdExtA, 260 FeatureStdExtF, 261 FeatureStdExtD, 262 FeatureStdExtC]>; 263 264def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM, 265 FeatureStdExtA, 266 FeatureStdExtF, 267 FeatureStdExtC]>; 268 269def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit, 270 FeatureStdExtM, 271 FeatureStdExtA, 272 FeatureStdExtF, 273 FeatureStdExtD, 274 FeatureStdExtC]>; 275 276//===----------------------------------------------------------------------===// 277// Define the RISC-V target. 278//===----------------------------------------------------------------------===// 279 280def RISCVInstrInfo : InstrInfo { 281 let guessInstructionProperties = 0; 282} 283 284def RISCVAsmParser : AsmParser { 285 let ShouldEmitMatchRegisterAltName = 1; 286 let AllowDuplicateRegisterNames = 1; 287} 288 289def RISCVAsmWriter : AsmWriter { 290 int PassSubtarget = 1; 291} 292 293def RISCV : Target { 294 let InstructionSet = RISCVInstrInfo; 295 let AssemblyParsers = [RISCVAsmParser]; 296 let AssemblyWriters = [RISCVAsmWriter]; 297 let AllowRegisterRenaming = 1; 298} 299