1//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// RISC-V subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15def FeatureStdExtM 16 : SubtargetFeature<"m", "HasStdExtM", "true", 17 "'M' (Integer Multiplication and Division)">; 18def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, 19 AssemblerPredicate<(all_of FeatureStdExtM), 20 "'M' (Integer Multiplication and Division)">; 21 22def FeatureStdExtA 23 : SubtargetFeature<"a", "HasStdExtA", "true", 24 "'A' (Atomic Instructions)">; 25def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, 26 AssemblerPredicate<(all_of FeatureStdExtA), 27 "'A' (Atomic Instructions)">; 28 29def FeatureStdExtF 30 : SubtargetFeature<"f", "HasStdExtF", "true", 31 "'F' (Single-Precision Floating-Point)">; 32def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, 33 AssemblerPredicate<(all_of FeatureStdExtF), 34 "'F' (Single-Precision Floating-Point)">; 35 36def FeatureStdExtD 37 : SubtargetFeature<"d", "HasStdExtD", "true", 38 "'D' (Double-Precision Floating-Point)", 39 [FeatureStdExtF]>; 40def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, 41 AssemblerPredicate<(all_of FeatureStdExtD), 42 "'D' (Double-Precision Floating-Point)">; 43 44def FeatureStdExtZfhmin 45 : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true", 46 "'Zfhmin' (Half-Precision Floating-Point Minimal)", 47 [FeatureStdExtF]>; 48def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">, 49 AssemblerPredicate<(all_of FeatureStdExtZfhmin), 50 "'Zfhmin' (Half-Precision Floating-Point Minimal)">; 51 52def FeatureStdExtZfh 53 : SubtargetFeature<"zfh", "HasStdExtZfh", "true", 54 "'Zfh' (Half-Precision Floating-Point)", 55 [FeatureStdExtZfhmin, FeatureStdExtF]>; 56def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">, 57 AssemblerPredicate<(all_of FeatureStdExtZfh), 58 "'Zfh' (Half-Precision Floating-Point)">; 59 60def FeatureStdExtC 61 : SubtargetFeature<"c", "HasStdExtC", "true", 62 "'C' (Compressed Instructions)">; 63def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, 64 AssemblerPredicate<(all_of FeatureStdExtC), 65 "'C' (Compressed Instructions)">; 66 67def FeatureStdExtZba 68 : SubtargetFeature<"zba", "HasStdExtZba", "true", 69 "'Zba' (Address Generation Instructions)">; 70def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">, 71 AssemblerPredicate<(all_of FeatureStdExtZba), 72 "'Zba' (Address Generation Instructions)">; 73def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">; 74 75def FeatureStdExtZbb 76 : SubtargetFeature<"zbb", "HasStdExtZbb", "true", 77 "'Zbb' (Basic Bit-Manipulation)">; 78def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, 79 AssemblerPredicate<(all_of FeatureStdExtZbb), 80 "'Zbb' (Basic Bit-Manipulation)">; 81 82def FeatureStdExtZbc 83 : SubtargetFeature<"zbc", "HasStdExtZbc", "true", 84 "'Zbc' (Carry-Less Multiplication)">; 85def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, 86 AssemblerPredicate<(all_of FeatureStdExtZbc), 87 "'Zbc' (Carry-Less Multiplication)">; 88 89def FeatureStdExtZbe 90 : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true", 91 "'Zbe' (Extract-Deposit 'Zb' Instructions)">; 92def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">, 93 AssemblerPredicate<(all_of FeatureStdExtZbe), 94 "'Zbe' (Extract-Deposit 'Zb' Instructions)">; 95 96def FeatureStdExtZbf 97 : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true", 98 "'Zbf' (Bit-Field 'Zb' Instructions)">; 99def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">, 100 AssemblerPredicate<(all_of FeatureStdExtZbf), 101 "'Zbf' (Bit-Field 'Zb' Instructions)">; 102 103def FeatureStdExtZbm 104 : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true", 105 "'Zbm' (Matrix 'Zb' Instructions)">; 106def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">, 107 AssemblerPredicate<(all_of FeatureStdExtZbm), 108 "'Zbm' (Matrix 'Zb' Instructions)">; 109 110def FeatureStdExtZbp 111 : SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true", 112 "'Zbp' (Permutation 'Zb' Instructions)">; 113def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">, 114 AssemblerPredicate<(all_of FeatureStdExtZbp), 115 "'Zbp' (Permutation 'Zb' Instructions)">; 116 117def FeatureStdExtZbr 118 : SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true", 119 "'Zbr' (Polynomial Reduction 'Zb' Instructions)">; 120def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">, 121 AssemblerPredicate<(all_of FeatureStdExtZbr), 122 "'Zbr' (Polynomial Reduction 'Zb' Instructions)">; 123 124def FeatureStdExtZbs 125 : SubtargetFeature<"zbs", "HasStdExtZbs", "true", 126 "'Zbs' (Single-Bit Instructions)">; 127def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, 128 AssemblerPredicate<(all_of FeatureStdExtZbs), 129 "'Zbs' (Single-Bit Instructions)">; 130 131def FeatureStdExtZbt 132 : SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true", 133 "'Zbt' (Ternary 'Zb' Instructions)">; 134def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">, 135 AssemblerPredicate<(all_of FeatureStdExtZbt), 136 "'Zbt' (Ternary 'Zb' Instructions)">; 137 138// Some instructions belong to both the basic and the permutation 139// subextensions. They should be enabled if either has been specified. 140def HasStdExtZbbOrZbp 141 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">, 142 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp), 143 "'Zbb' (Basic Bit-Manipulation) or " 144 "'Zbp' (Permutation 'Zb' Instructions)">; 145 146def FeatureStdExtZbkb 147 : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true", 148 "'Zbkb' (Bitmanip instructions for Cryptography)">; 149def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">, 150 AssemblerPredicate<(all_of FeatureStdExtZbkb), 151 "'Zbkb' (Bitmanip instructions for Cryptography)">; 152 153def FeatureStdExtZbkx 154 : SubtargetFeature<"zbkx", "HasStdExtZbkx", "true", 155 "'Zbkx' (Crossbar permutation instructions)">; 156def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">, 157 AssemblerPredicate<(all_of FeatureStdExtZbkx), 158 "'Zbkx' (Crossbar permutation instructions)">; 159 160def HasStdExtZbpOrZbkx 161 : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkx()">, 162 AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkx), 163 "'Zbp' (Permutation 'Zb' Instructions) or " 164 "'Zbkx' (Crossbar permutation instructions)">; 165 166def HasStdExtZbpOrZbkb 167 : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">, 168 AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkb), 169 "'Zbp' (Permutation 'Zb' Instructions) or " 170 "'Zbkb' (Bitmanip instructions for Cryptography)">; 171 172def HasStdExtZbbOrZbkb 173 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">, 174 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb), 175 "'Zbb' (Basic Bit-Manipulation) or " 176 "'Zbkb' (Bitmanip instructions for Cryptography)">; 177 178def HasStdExtZbbOrZbpOrZbkb 179 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">, 180 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp, FeatureStdExtZbkb), 181 "'Zbb' (Basic Bit-Manipulation) or " 182 "'Zbp' (Permutation 'Zb' Instructions) or " 183 "'Zbkb' (Bitmanip instructions for Cryptography)">; 184 185// The Carry-less multiply subextension for cryptography is a subset of basic carry-less multiply subextension. The former should be enabled if the latter is enabled. 186def FeatureStdExtZbkc 187 : SubtargetFeature<"zbkc", "HasStdExtZbkc", "true", 188 "'Zbkc' (Carry-less multiply instructions for Cryptography)">; 189def HasStdExtZbkc 190 : Predicate<"Subtarget->hasStdExtZbkc()">, 191 AssemblerPredicate<(all_of FeatureStdExtZbkc), 192 "'Zbkc' (Carry-less multiply instructions for Cryptography)">; 193 194def HasStdExtZbcOrZbkc 195 : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">, 196 AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc), 197 "'Zbc' (Carry-Less Multiplication) or " 198 "'Zbkc' (Carry-less multiply instructions for Cryptography)">; 199 200def FeatureStdExtZknd 201 : SubtargetFeature<"zknd", "HasStdExtZknd", "true", 202 "'Zknd' (NIST Suite: AES Decryption)">; 203def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">, 204 AssemblerPredicate<(all_of FeatureStdExtZknd), 205 "'Zknd' (NIST Suite: AES Decryption)">; 206 207def FeatureStdExtZkne 208 : SubtargetFeature<"zkne", "HasStdExtZkne", "true", 209 "'Zkne' (NIST Suite: AES Encryption)">; 210def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">, 211 AssemblerPredicate<(all_of FeatureStdExtZkne), 212 "'Zkne' (NIST Suite: AES Encryption)">; 213 214// Some instructions belong to both Zknd and Zkne subextensions. 215// They should be enabled if either has been specified. 216def HasStdExtZkndOrZkne 217 : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">, 218 AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne), 219 "'Zknd' (NIST Suite: AES Decryption) or " 220 "'Zkne' (NIST Suite: AES Encryption)">; 221 222def FeatureStdExtZknh 223 : SubtargetFeature<"zknh", "HasStdExtZknh", "true", 224 "'Zknh' (NIST Suite: Hash Function Instructions)">; 225def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">, 226 AssemblerPredicate<(all_of FeatureStdExtZknh), 227 "'Zknh' (NIST Suite: Hash Function Instructions)">; 228 229def FeatureStdExtZksed 230 : SubtargetFeature<"zksed", "HasStdExtZksed", "true", 231 "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; 232def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">, 233 AssemblerPredicate<(all_of FeatureStdExtZksed), 234 "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; 235 236def FeatureStdExtZksh 237 : SubtargetFeature<"zksh", "HasStdExtZksh", "true", 238 "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; 239def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">, 240 AssemblerPredicate<(all_of FeatureStdExtZksh), 241 "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; 242 243def FeatureStdExtZkr 244 : SubtargetFeature<"zkr", "HasStdExtZkr", "true", 245 "'Zkr' (Entropy Source Extension)">; 246def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">, 247 AssemblerPredicate<(all_of FeatureStdExtZkr), 248 "'Zkr' (Entropy Source Extension)">; 249 250def FeatureStdExtZkn 251 : SubtargetFeature<"zkn", "HasStdExtZkn", "true", 252 "'Zkn' (NIST Algorithm Suite)", 253 [FeatureStdExtZbkb, 254 FeatureStdExtZbkc, 255 FeatureStdExtZbkx, 256 FeatureStdExtZkne, 257 FeatureStdExtZknd, 258 FeatureStdExtZknh]>; 259 260def FeatureStdExtZks 261 : SubtargetFeature<"zks", "HasStdExtZks", "true", 262 "'Zks' (ShangMi Algorithm Suite)", 263 [FeatureStdExtZbkb, 264 FeatureStdExtZbkc, 265 FeatureStdExtZbkx, 266 FeatureStdExtZksed, 267 FeatureStdExtZksh]>; 268 269def FeatureStdExtZkt 270 : SubtargetFeature<"zkt", "HasStdExtZkt", "true", 271 "'Zkt' (Data Independent Execution Latency)">; 272 273def FeatureStdExtZk 274 : SubtargetFeature<"zk", "HasStdExtZk", "true", 275 "'Zk' (Standard scalar cryptography extension)", 276 [FeatureStdExtZkn, 277 FeatureStdExtZkr, 278 FeatureStdExtZkt]>; 279 280def FeatureNoRVCHints 281 : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", 282 "Disable RVC Hint Instructions.">; 283def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, 284 AssemblerPredicate<(all_of(not FeatureNoRVCHints)), 285 "RVC Hint Instructions">; 286 287def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "ExtZvl::Zvl32b", 288 "'Zvl' (Minimum Vector Length) 32">; 289 290foreach i = { 6-15 } in { 291 defvar I = !shl(1, i); 292 def FeatureStdExtZvl#I#b : 293 SubtargetFeature<"zvl"#I#"b", "ZvlLen", "ExtZvl::Zvl"#I#"b", 294 "'Zvl' (Minimum Vector Length) "#I, 295 [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>; 296} 297 298def FeatureStdExtZve32x 299 : SubtargetFeature<"zve32x", "HasStdExtZve32x", "true", 300 "'Zve32x' (Vector Extensions for Embedded Processors " 301 "with maximal 32 EEW)", 302 [FeatureStdExtZvl32b]>; 303 304def FeatureStdExtZve32f 305 : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true", 306 "'Zve32f' (Vector Extensions for Embedded Processors " 307 "with maximal 32 EEW and F extension)", 308 [FeatureStdExtZve32x]>; 309 310def FeatureStdExtZve64x 311 : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true", 312 "'Zve64x' (Vector Extensions for Embedded Processors " 313 "with maximal 64 EEW)", [FeatureStdExtZve32x, FeatureStdExtZvl64b]>; 314 315def FeatureStdExtZve64f 316 : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true", 317 "'Zve64f' (Vector Extensions for Embedded Processors " 318 "with maximal 64 EEW and F extension)", 319 [FeatureStdExtZve32f, FeatureStdExtZve64x]>; 320 321def FeatureStdExtZve64d 322 : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true", 323 "'Zve64d' (Vector Extensions for Embedded Processors " 324 "with maximal 64 EEW, F and D extension)", 325 [FeatureStdExtZve64f]>; 326 327def FeatureStdExtV 328 : SubtargetFeature<"v", "HasStdExtV", "true", 329 "'V' (Vector Extension for Application Processors)", 330 [FeatureStdExtZvl128b, FeatureStdExtF, FeatureStdExtD]>; 331 332def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">, 333 AssemblerPredicate< 334 (any_of FeatureStdExtZve32x, FeatureStdExtV), 335 "'V' (Vector Extension for Application Processors), 'Zve32x' or " 336 "'Zve64x' (Vector Extensions for Embedded Processors)">; 337def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">, 338 AssemblerPredicate< 339 (any_of FeatureStdExtZve64x, FeatureStdExtV), 340 "'V' (Vector Extension for Application Processors) or 'Zve64x' " 341 "(Vector Extensions for Embedded Processors)">; 342def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">, 343 AssemblerPredicate< 344 (any_of FeatureStdExtZve32f, FeatureStdExtV), 345 "'V' (Vector Extension for Application Processors), 'Zve32f', " 346 "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">; 347 348def Feature64Bit 349 : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; 350def IsRV64 : Predicate<"Subtarget->is64Bit()">, 351 AssemblerPredicate<(all_of Feature64Bit), 352 "RV64I Base Instruction Set">; 353def IsRV32 : Predicate<"!Subtarget->is64Bit()">, 354 AssemblerPredicate<(all_of (not Feature64Bit)), 355 "RV32I Base Instruction Set">; 356 357defvar RV32 = DefaultMode; 358def RV64 : HwMode<"+64bit">; 359 360def FeatureRV32E 361 : SubtargetFeature<"e", "IsRV32E", "true", 362 "Implements RV32E (provides 16 rather than 32 GPRs)">; 363def IsRV32E : Predicate<"Subtarget->isRV32E()">, 364 AssemblerPredicate<(all_of FeatureRV32E)>; 365 366def FeatureRelax 367 : SubtargetFeature<"relax", "EnableLinkerRelax", "true", 368 "Enable Linker relaxation.">; 369 370foreach i = {1-31} in 371 def FeatureReserveX#i : 372 SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", 373 "true", "Reserve X"#i>; 374 375def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore", 376 "true", "Enable save/restore.">; 377 378def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", 379 "SiFive 7-Series processors">; 380 381//===----------------------------------------------------------------------===// 382// Named operands for CSR instructions. 383//===----------------------------------------------------------------------===// 384 385include "RISCVSystemOperands.td" 386 387//===----------------------------------------------------------------------===// 388// Registers, calling conventions, instruction descriptions. 389//===----------------------------------------------------------------------===// 390 391include "RISCVSchedule.td" 392include "RISCVRegisterInfo.td" 393include "RISCVCallingConv.td" 394include "RISCVInstrInfo.td" 395include "RISCVRegisterBanks.td" 396include "RISCVSchedRocket.td" 397include "RISCVSchedSiFive7.td" 398 399//===----------------------------------------------------------------------===// 400// RISC-V processors supported. 401//===----------------------------------------------------------------------===// 402 403def : ProcessorModel<"generic-rv32", NoSchedModel, []>; 404def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; 405 406def : ProcessorModel<"rocket-rv32", RocketModel, []>; 407def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>; 408 409def : ProcessorModel<"sifive-7-rv32", SiFive7Model, [], 410 [TuneSiFive7]>; 411def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit], 412 [TuneSiFive7]>; 413 414def : ProcessorModel<"sifive-e20", RocketModel, [FeatureStdExtM, 415 FeatureStdExtC]>; 416 417def : ProcessorModel<"sifive-e21", RocketModel, [FeatureStdExtM, 418 FeatureStdExtA, 419 FeatureStdExtC]>; 420 421def : ProcessorModel<"sifive-e24", RocketModel, [FeatureStdExtM, 422 FeatureStdExtA, 423 FeatureStdExtF, 424 FeatureStdExtC]>; 425 426def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM, 427 FeatureStdExtA, 428 FeatureStdExtC]>; 429 430def : ProcessorModel<"sifive-e34", RocketModel, [FeatureStdExtM, 431 FeatureStdExtA, 432 FeatureStdExtF, 433 FeatureStdExtC]>; 434 435def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM, 436 FeatureStdExtA, 437 FeatureStdExtF, 438 FeatureStdExtC], 439 [TuneSiFive7]>; 440 441def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit, 442 FeatureStdExtM, 443 FeatureStdExtA, 444 FeatureStdExtC]>; 445 446def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit, 447 FeatureStdExtM, 448 FeatureStdExtA, 449 FeatureStdExtC]>; 450 451def : ProcessorModel<"sifive-s54", RocketModel, [Feature64Bit, 452 FeatureStdExtM, 453 FeatureStdExtA, 454 FeatureStdExtF, 455 FeatureStdExtD, 456 FeatureStdExtC]>; 457 458def : ProcessorModel<"sifive-s76", SiFive7Model, [Feature64Bit, 459 FeatureStdExtM, 460 FeatureStdExtA, 461 FeatureStdExtF, 462 FeatureStdExtD, 463 FeatureStdExtC], 464 [TuneSiFive7]>; 465 466def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit, 467 FeatureStdExtM, 468 FeatureStdExtA, 469 FeatureStdExtF, 470 FeatureStdExtD, 471 FeatureStdExtC]>; 472 473def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit, 474 FeatureStdExtM, 475 FeatureStdExtA, 476 FeatureStdExtF, 477 FeatureStdExtD, 478 FeatureStdExtC], 479 [TuneSiFive7]>; 480 481//===----------------------------------------------------------------------===// 482// Define the RISC-V target. 483//===----------------------------------------------------------------------===// 484 485def RISCVInstrInfo : InstrInfo { 486 let guessInstructionProperties = 0; 487} 488 489def RISCVAsmParser : AsmParser { 490 let ShouldEmitMatchRegisterAltName = 1; 491 let AllowDuplicateRegisterNames = 1; 492} 493 494def RISCVAsmWriter : AsmWriter { 495 int PassSubtarget = 1; 496} 497 498def RISCV : Target { 499 let InstructionSet = RISCVInstrInfo; 500 let AssemblyParsers = [RISCVAsmParser]; 501 let AssemblyWriters = [RISCVAsmWriter]; 502 let AllowRegisterRenaming = 1; 503} 504