1*0b57cec5SDimitry Andric//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric 9*0b57cec5SDimitry Andricinclude "llvm/Target/Target.td" 10*0b57cec5SDimitry Andric 11*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric// RISC-V subtarget features and instruction predicates. 13*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andricdef FeatureStdExtM 16*0b57cec5SDimitry Andric : SubtargetFeature<"m", "HasStdExtM", "true", 17*0b57cec5SDimitry Andric "'M' (Integer Multiplication and Division)">; 18*0b57cec5SDimitry Andricdef HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, 19*0b57cec5SDimitry Andric AssemblerPredicate<"FeatureStdExtM">; 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andricdef FeatureStdExtA 22*0b57cec5SDimitry Andric : SubtargetFeature<"a", "HasStdExtA", "true", 23*0b57cec5SDimitry Andric "'A' (Atomic Instructions)">; 24*0b57cec5SDimitry Andricdef HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, 25*0b57cec5SDimitry Andric AssemblerPredicate<"FeatureStdExtA">; 26*0b57cec5SDimitry Andric 27*0b57cec5SDimitry Andricdef FeatureStdExtF 28*0b57cec5SDimitry Andric : SubtargetFeature<"f", "HasStdExtF", "true", 29*0b57cec5SDimitry Andric "'F' (Single-Precision Floating-Point)">; 30*0b57cec5SDimitry Andricdef HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, 31*0b57cec5SDimitry Andric AssemblerPredicate<"FeatureStdExtF">; 32*0b57cec5SDimitry Andric 33*0b57cec5SDimitry Andricdef FeatureStdExtD 34*0b57cec5SDimitry Andric : SubtargetFeature<"d", "HasStdExtD", "true", 35*0b57cec5SDimitry Andric "'D' (Double-Precision Floating-Point)", 36*0b57cec5SDimitry Andric [FeatureStdExtF]>; 37*0b57cec5SDimitry Andricdef HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, 38*0b57cec5SDimitry Andric AssemblerPredicate<"FeatureStdExtD">; 39*0b57cec5SDimitry Andric 40*0b57cec5SDimitry Andricdef FeatureStdExtC 41*0b57cec5SDimitry Andric : SubtargetFeature<"c", "HasStdExtC", "true", 42*0b57cec5SDimitry Andric "'C' (Compressed Instructions)">; 43*0b57cec5SDimitry Andricdef HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, 44*0b57cec5SDimitry Andric AssemblerPredicate<"FeatureStdExtC">; 45*0b57cec5SDimitry Andric 46*0b57cec5SDimitry Andric 47*0b57cec5SDimitry Andricdef Feature64Bit 48*0b57cec5SDimitry Andric : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; 49*0b57cec5SDimitry Andricdef IsRV64 : Predicate<"Subtarget->is64Bit()">, 50*0b57cec5SDimitry Andric AssemblerPredicate<"Feature64Bit">; 51*0b57cec5SDimitry Andricdef IsRV32 : Predicate<"!Subtarget->is64Bit()">, 52*0b57cec5SDimitry Andric AssemblerPredicate<"!Feature64Bit">; 53*0b57cec5SDimitry Andric 54*0b57cec5SDimitry Andricdef RV64 : HwMode<"+64bit">; 55*0b57cec5SDimitry Andricdef RV32 : HwMode<"-64bit">; 56*0b57cec5SDimitry Andric 57*0b57cec5SDimitry Andricdef FeatureRV32E 58*0b57cec5SDimitry Andric : SubtargetFeature<"e", "IsRV32E", "true", 59*0b57cec5SDimitry Andric "Implements RV32E (provides 16 rather than 32 GPRs)">; 60*0b57cec5SDimitry Andricdef IsRV32E : Predicate<"Subtarget->isRV32E()">, 61*0b57cec5SDimitry Andric AssemblerPredicate<"FeatureRV32E">; 62*0b57cec5SDimitry Andric 63*0b57cec5SDimitry Andricdef FeatureRelax 64*0b57cec5SDimitry Andric : SubtargetFeature<"relax", "EnableLinkerRelax", "true", 65*0b57cec5SDimitry Andric "Enable Linker relaxation.">; 66*0b57cec5SDimitry Andric 67*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 68*0b57cec5SDimitry Andric// Named operands for CSR instructions. 69*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 70*0b57cec5SDimitry Andric 71*0b57cec5SDimitry Andricinclude "RISCVSystemOperands.td" 72*0b57cec5SDimitry Andric 73*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 74*0b57cec5SDimitry Andric// Registers, calling conventions, instruction descriptions. 75*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 76*0b57cec5SDimitry Andric 77*0b57cec5SDimitry Andricinclude "RISCVRegisterInfo.td" 78*0b57cec5SDimitry Andricinclude "RISCVCallingConv.td" 79*0b57cec5SDimitry Andricinclude "RISCVInstrInfo.td" 80*0b57cec5SDimitry Andric 81*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 82*0b57cec5SDimitry Andric// RISC-V processors supported. 83*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 84*0b57cec5SDimitry Andric 85*0b57cec5SDimitry Andricdef : ProcessorModel<"generic-rv32", NoSchedModel, []>; 86*0b57cec5SDimitry Andric 87*0b57cec5SDimitry Andricdef : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; 88*0b57cec5SDimitry Andric 89*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 90*0b57cec5SDimitry Andric// Define the RISC-V target. 91*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 92*0b57cec5SDimitry Andric 93*0b57cec5SDimitry Andricdef RISCVInstrInfo : InstrInfo { 94*0b57cec5SDimitry Andric let guessInstructionProperties = 0; 95*0b57cec5SDimitry Andric} 96*0b57cec5SDimitry Andric 97*0b57cec5SDimitry Andricdef RISCVAsmParser : AsmParser { 98*0b57cec5SDimitry Andric let ShouldEmitMatchRegisterAltName = 1; 99*0b57cec5SDimitry Andric let AllowDuplicateRegisterNames = 1; 100*0b57cec5SDimitry Andric} 101*0b57cec5SDimitry Andric 102*0b57cec5SDimitry Andricdef RISCVAsmWriter : AsmWriter { 103*0b57cec5SDimitry Andric int PassSubtarget = 1; 104*0b57cec5SDimitry Andric} 105*0b57cec5SDimitry Andric 106*0b57cec5SDimitry Andricdef RISCV : Target { 107*0b57cec5SDimitry Andric let InstructionSet = RISCVInstrInfo; 108*0b57cec5SDimitry Andric let AssemblyParsers = [RISCVAsmParser]; 109*0b57cec5SDimitry Andric let AssemblyWriters = [RISCVAsmWriter]; 110*0b57cec5SDimitry Andric let AllowRegisterRenaming = 1; 111*0b57cec5SDimitry Andric} 112