1*06c3fb27SDimitry Andric//===-- RISCV.td - Describe the RISC-V Target Machine ------*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 90b57cec5SDimitry Andricinclude "llvm/Target/Target.td" 100b57cec5SDimitry Andric 110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric// RISC-V subtarget features and instruction predicates. 130b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 140b57cec5SDimitry Andric 15bdd1243dSDimitry Andricinclude "RISCVFeatures.td" 1604eeddc0SDimitry Andric 170b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 180b57cec5SDimitry Andric// Named operands for CSR instructions. 190b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 200b57cec5SDimitry Andric 210b57cec5SDimitry Andricinclude "RISCVSystemOperands.td" 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 240b57cec5SDimitry Andric// Registers, calling conventions, instruction descriptions. 250b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 260b57cec5SDimitry Andric 2713138422SDimitry Andricinclude "RISCVSchedule.td" 280b57cec5SDimitry Andricinclude "RISCVRegisterInfo.td" 290b57cec5SDimitry Andricinclude "RISCVCallingConv.td" 300b57cec5SDimitry Andricinclude "RISCVInstrInfo.td" 31bdd1243dSDimitry Andricinclude "GISel/RISCVRegisterBanks.td" 32bdd1243dSDimitry Andric 33bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 34bdd1243dSDimitry Andric// RISC-V Scheduling Models 35bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 36bdd1243dSDimitry Andric 37e8d8bef9SDimitry Andricinclude "RISCVSchedRocket.td" 38e8d8bef9SDimitry Andricinclude "RISCVSchedSiFive7.td" 39bdd1243dSDimitry Andricinclude "RISCVSchedSyntacoreSCR1.td" 400b57cec5SDimitry Andric 410b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 420b57cec5SDimitry Andric// RISC-V processors supported. 430b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 440b57cec5SDimitry Andric 45bdd1243dSDimitry Andricinclude "RISCVProcessors.td" 4613138422SDimitry Andric 470b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 480b57cec5SDimitry Andric// Define the RISC-V target. 490b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 500b57cec5SDimitry Andric 510b57cec5SDimitry Andricdef RISCVInstrInfo : InstrInfo { 520b57cec5SDimitry Andric let guessInstructionProperties = 0; 530b57cec5SDimitry Andric} 540b57cec5SDimitry Andric 550b57cec5SDimitry Andricdef RISCVAsmParser : AsmParser { 560b57cec5SDimitry Andric let ShouldEmitMatchRegisterAltName = 1; 570b57cec5SDimitry Andric let AllowDuplicateRegisterNames = 1; 580b57cec5SDimitry Andric} 590b57cec5SDimitry Andric 600b57cec5SDimitry Andricdef RISCVAsmWriter : AsmWriter { 610b57cec5SDimitry Andric int PassSubtarget = 1; 620b57cec5SDimitry Andric} 630b57cec5SDimitry Andric 640b57cec5SDimitry Andricdef RISCV : Target { 650b57cec5SDimitry Andric let InstructionSet = RISCVInstrInfo; 660b57cec5SDimitry Andric let AssemblyParsers = [RISCVAsmParser]; 670b57cec5SDimitry Andric let AssemblyWriters = [RISCVAsmWriter]; 680b57cec5SDimitry Andric let AllowRegisterRenaming = 1; 690b57cec5SDimitry Andric} 70