xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.h (revision 1323ec571215a77ddd21294f0871979d5ad6b992)
1 //===-- RISCV.h - Top-level interface for RISCV -----------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the entry points for global functions defined in the LLVM
10 // RISC-V back-end.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_RISCV_RISCV_H
15 #define LLVM_LIB_TARGET_RISCV_RISCV_H
16 
17 #include "MCTargetDesc/RISCVBaseInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 
20 namespace llvm {
21 class RISCVRegisterBankInfo;
22 class RISCVSubtarget;
23 class RISCVTargetMachine;
24 class AsmPrinter;
25 class FunctionPass;
26 class InstructionSelector;
27 class MCInst;
28 class MCOperand;
29 class MachineInstr;
30 class MachineOperand;
31 class PassRegistry;
32 
33 bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
34                                     AsmPrinter &AP);
35 bool LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
36                                          MCOperand &MCOp, const AsmPrinter &AP);
37 
38 FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM);
39 
40 FunctionPass *createRISCVMergeBaseOffsetOptPass();
41 void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
42 
43 FunctionPass *createRISCVExpandPseudoPass();
44 void initializeRISCVExpandPseudoPass(PassRegistry &);
45 
46 FunctionPass *createRISCVExpandAtomicPseudoPass();
47 void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
48 
49 FunctionPass *createRISCVInsertVSETVLIPass();
50 void initializeRISCVInsertVSETVLIPass(PassRegistry &);
51 
52 InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
53                                                     RISCVSubtarget &,
54                                                     RISCVRegisterBankInfo &);
55 }
56 
57 #endif
58