10b57cec5SDimitry Andric //===-- RISCV.h - Top-level interface for RISCV -----------------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file contains the entry points for global functions defined in the LLVM 100b57cec5SDimitry Andric // RISC-V back-end. 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_RISCV_RISCV_H 150b57cec5SDimitry Andric #define LLVM_LIB_TARGET_RISCV_RISCV_H 160b57cec5SDimitry Andric 17e8d8bef9SDimitry Andric #include "MCTargetDesc/RISCVBaseInfo.h" 180b57cec5SDimitry Andric #include "llvm/Target/TargetMachine.h" 190b57cec5SDimitry Andric 200b57cec5SDimitry Andric namespace llvm { 218bcb0991SDimitry Andric class RISCVRegisterBankInfo; 228bcb0991SDimitry Andric class RISCVSubtarget; 230b57cec5SDimitry Andric class RISCVTargetMachine; 240b57cec5SDimitry Andric class AsmPrinter; 250b57cec5SDimitry Andric class FunctionPass; 268bcb0991SDimitry Andric class InstructionSelector; 270b57cec5SDimitry Andric class MCInst; 280b57cec5SDimitry Andric class MCOperand; 290b57cec5SDimitry Andric class MachineInstr; 300b57cec5SDimitry Andric class MachineOperand; 310b57cec5SDimitry Andric class PassRegistry; 320b57cec5SDimitry Andric 33*fcaf7f86SDimitry Andric FunctionPass *createRISCVCodeGenPreparePass(); 34*fcaf7f86SDimitry Andric void initializeRISCVCodeGenPreparePass(PassRegistry &); 35*fcaf7f86SDimitry Andric 36fe6060f1SDimitry Andric bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, 37fe6060f1SDimitry Andric AsmPrinter &AP); 3881ad6265SDimitry Andric bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO, 390b57cec5SDimitry Andric MCOperand &MCOp, const AsmPrinter &AP); 400b57cec5SDimitry Andric 4181ad6265SDimitry Andric FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM, 4281ad6265SDimitry Andric CodeGenOpt::Level OptLevel); 4381ad6265SDimitry Andric 4481ad6265SDimitry Andric FunctionPass *createRISCVMakeCompressibleOptPass(); 4581ad6265SDimitry Andric void initializeRISCVMakeCompressibleOptPass(PassRegistry &); 460b57cec5SDimitry Andric 47349cc55cSDimitry Andric FunctionPass *createRISCVGatherScatterLoweringPass(); 48349cc55cSDimitry Andric void initializeRISCVGatherScatterLoweringPass(PassRegistry &); 49349cc55cSDimitry Andric 5004eeddc0SDimitry Andric FunctionPass *createRISCVSExtWRemovalPass(); 5104eeddc0SDimitry Andric void initializeRISCVSExtWRemovalPass(PassRegistry &); 5204eeddc0SDimitry Andric 530b57cec5SDimitry Andric FunctionPass *createRISCVMergeBaseOffsetOptPass(); 540b57cec5SDimitry Andric void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &); 550b57cec5SDimitry Andric 560b57cec5SDimitry Andric FunctionPass *createRISCVExpandPseudoPass(); 570b57cec5SDimitry Andric void initializeRISCVExpandPseudoPass(PassRegistry &); 588bcb0991SDimitry Andric 595ffd83dbSDimitry Andric FunctionPass *createRISCVExpandAtomicPseudoPass(); 605ffd83dbSDimitry Andric void initializeRISCVExpandAtomicPseudoPass(PassRegistry &); 615ffd83dbSDimitry Andric 62fe6060f1SDimitry Andric FunctionPass *createRISCVInsertVSETVLIPass(); 63fe6060f1SDimitry Andric void initializeRISCVInsertVSETVLIPass(PassRegistry &); 64e8d8bef9SDimitry Andric 6581ad6265SDimitry Andric FunctionPass *createRISCVRedundantCopyEliminationPass(); 6681ad6265SDimitry Andric void initializeRISCVRedundantCopyEliminationPass(PassRegistry &); 6781ad6265SDimitry Andric 688bcb0991SDimitry Andric InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &, 698bcb0991SDimitry Andric RISCVSubtarget &, 708bcb0991SDimitry Andric RISCVRegisterBankInfo &); 710b57cec5SDimitry Andric } 720b57cec5SDimitry Andric 730b57cec5SDimitry Andric #endif 74