10b57cec5SDimitry Andric //===-- RISCV.h - Top-level interface for RISCV -----------------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file contains the entry points for global functions defined in the LLVM 100b57cec5SDimitry Andric // RISC-V back-end. 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_RISCV_RISCV_H 150b57cec5SDimitry Andric #define LLVM_LIB_TARGET_RISCV_RISCV_H 160b57cec5SDimitry Andric 17*e8d8bef9SDimitry Andric #include "MCTargetDesc/RISCVBaseInfo.h" 180b57cec5SDimitry Andric #include "llvm/Target/TargetMachine.h" 190b57cec5SDimitry Andric 200b57cec5SDimitry Andric namespace llvm { 218bcb0991SDimitry Andric class RISCVRegisterBankInfo; 228bcb0991SDimitry Andric class RISCVSubtarget; 230b57cec5SDimitry Andric class RISCVTargetMachine; 240b57cec5SDimitry Andric class AsmPrinter; 250b57cec5SDimitry Andric class FunctionPass; 268bcb0991SDimitry Andric class InstructionSelector; 270b57cec5SDimitry Andric class MCInst; 280b57cec5SDimitry Andric class MCOperand; 290b57cec5SDimitry Andric class MachineInstr; 300b57cec5SDimitry Andric class MachineOperand; 310b57cec5SDimitry Andric class PassRegistry; 320b57cec5SDimitry Andric 330b57cec5SDimitry Andric void LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, 340b57cec5SDimitry Andric const AsmPrinter &AP); 350b57cec5SDimitry Andric bool LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO, 360b57cec5SDimitry Andric MCOperand &MCOp, const AsmPrinter &AP); 370b57cec5SDimitry Andric 380b57cec5SDimitry Andric FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM); 390b57cec5SDimitry Andric 400b57cec5SDimitry Andric FunctionPass *createRISCVMergeBaseOffsetOptPass(); 410b57cec5SDimitry Andric void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &); 420b57cec5SDimitry Andric 430b57cec5SDimitry Andric FunctionPass *createRISCVExpandPseudoPass(); 440b57cec5SDimitry Andric void initializeRISCVExpandPseudoPass(PassRegistry &); 458bcb0991SDimitry Andric 465ffd83dbSDimitry Andric FunctionPass *createRISCVExpandAtomicPseudoPass(); 475ffd83dbSDimitry Andric void initializeRISCVExpandAtomicPseudoPass(PassRegistry &); 485ffd83dbSDimitry Andric 49*e8d8bef9SDimitry Andric FunctionPass *createRISCVCleanupVSETVLIPass(); 50*e8d8bef9SDimitry Andric void initializeRISCVCleanupVSETVLIPass(PassRegistry &); 51*e8d8bef9SDimitry Andric 528bcb0991SDimitry Andric InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &, 538bcb0991SDimitry Andric RISCVSubtarget &, 548bcb0991SDimitry Andric RISCVRegisterBankInfo &); 550b57cec5SDimitry Andric } 560b57cec5SDimitry Andric 570b57cec5SDimitry Andric #endif 58