xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.h (revision 0b57cec536236d46e3dba9bd041533462f33dbb7)
1*0b57cec5SDimitry Andric //===-- RISCV.h - Top-level interface for RISCV -----------------*- C++ -*-===//
2*0b57cec5SDimitry Andric //
3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0b57cec5SDimitry Andric //
7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
8*0b57cec5SDimitry Andric //
9*0b57cec5SDimitry Andric // This file contains the entry points for global functions defined in the LLVM
10*0b57cec5SDimitry Andric // RISC-V back-end.
11*0b57cec5SDimitry Andric //
12*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
13*0b57cec5SDimitry Andric 
14*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_RISCV_RISCV_H
15*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_RISCV_RISCV_H
16*0b57cec5SDimitry Andric 
17*0b57cec5SDimitry Andric #include "Utils/RISCVBaseInfo.h"
18*0b57cec5SDimitry Andric #include "llvm/Target/TargetMachine.h"
19*0b57cec5SDimitry Andric 
20*0b57cec5SDimitry Andric namespace llvm {
21*0b57cec5SDimitry Andric class RISCVTargetMachine;
22*0b57cec5SDimitry Andric class AsmPrinter;
23*0b57cec5SDimitry Andric class FunctionPass;
24*0b57cec5SDimitry Andric class MCInst;
25*0b57cec5SDimitry Andric class MCOperand;
26*0b57cec5SDimitry Andric class MachineInstr;
27*0b57cec5SDimitry Andric class MachineOperand;
28*0b57cec5SDimitry Andric class PassRegistry;
29*0b57cec5SDimitry Andric 
30*0b57cec5SDimitry Andric void LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
31*0b57cec5SDimitry Andric                                     const AsmPrinter &AP);
32*0b57cec5SDimitry Andric bool LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
33*0b57cec5SDimitry Andric                                          MCOperand &MCOp, const AsmPrinter &AP);
34*0b57cec5SDimitry Andric 
35*0b57cec5SDimitry Andric FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM);
36*0b57cec5SDimitry Andric 
37*0b57cec5SDimitry Andric FunctionPass *createRISCVMergeBaseOffsetOptPass();
38*0b57cec5SDimitry Andric void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
39*0b57cec5SDimitry Andric 
40*0b57cec5SDimitry Andric FunctionPass *createRISCVExpandPseudoPass();
41*0b57cec5SDimitry Andric void initializeRISCVExpandPseudoPass(PassRegistry &);
42*0b57cec5SDimitry Andric }
43*0b57cec5SDimitry Andric 
44*0b57cec5SDimitry Andric #endif
45