1 //===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides RISC-V specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVTargetStreamer.h" 14 #include "RISCVBaseInfo.h" 15 #include "RISCVMCTargetDesc.h" 16 #include "llvm/MC/MCSymbol.h" 17 #include "llvm/Support/FormattedStream.h" 18 #include "llvm/Support/RISCVAttributes.h" 19 #include "llvm/Support/RISCVISAInfo.h" 20 21 using namespace llvm; 22 23 RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} 24 25 void RISCVTargetStreamer::finish() { finishAttributeSection(); } 26 void RISCVTargetStreamer::reset() {} 27 28 void RISCVTargetStreamer::emitDirectiveOptionPush() {} 29 void RISCVTargetStreamer::emitDirectiveOptionPop() {} 30 void RISCVTargetStreamer::emitDirectiveOptionPIC() {} 31 void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {} 32 void RISCVTargetStreamer::emitDirectiveOptionRVC() {} 33 void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {} 34 void RISCVTargetStreamer::emitDirectiveOptionRelax() {} 35 void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {} 36 void RISCVTargetStreamer::emitDirectiveOptionArch( 37 ArrayRef<RISCVOptionArchArg> Args) {} 38 void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {} 39 void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {} 40 void RISCVTargetStreamer::finishAttributeSection() {} 41 void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute, 42 StringRef String) {} 43 void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute, 44 unsigned IntValue, 45 StringRef StringValue) {} 46 void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) { 47 assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI"); 48 TargetABI = ABI; 49 } 50 51 void RISCVTargetStreamer::setFlagsFromFeatures(const MCSubtargetInfo &STI) { 52 HasRVC = STI.hasFeature(RISCV::FeatureStdExtC); 53 HasTSO = STI.hasFeature(RISCV::FeatureStdExtZtso); 54 } 55 56 void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI, 57 bool EmitStackAlign) { 58 if (EmitStackAlign) { 59 if (TargetABI == RISCVABI::ABI_ILP32E) 60 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4); 61 else if (TargetABI == RISCVABI::ABI_LP64E) 62 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_8); 63 else 64 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16); 65 } 66 67 auto ParseResult = RISCVFeatures::parseFeatureBits( 68 STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits()); 69 if (!ParseResult) { 70 report_fatal_error(ParseResult.takeError()); 71 } else { 72 auto &ISAInfo = *ParseResult; 73 emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString()); 74 } 75 } 76 77 // This part is for ascii assembly output 78 RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S, 79 formatted_raw_ostream &OS) 80 : RISCVTargetStreamer(S), OS(OS) {} 81 82 void RISCVTargetAsmStreamer::emitDirectiveOptionPush() { 83 OS << "\t.option\tpush\n"; 84 } 85 86 void RISCVTargetAsmStreamer::emitDirectiveOptionPop() { 87 OS << "\t.option\tpop\n"; 88 } 89 90 void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() { 91 OS << "\t.option\tpic\n"; 92 } 93 94 void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() { 95 OS << "\t.option\tnopic\n"; 96 } 97 98 void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() { 99 OS << "\t.option\trvc\n"; 100 } 101 102 void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() { 103 OS << "\t.option\tnorvc\n"; 104 } 105 106 void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() { 107 OS << "\t.option\trelax\n"; 108 } 109 110 void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() { 111 OS << "\t.option\tnorelax\n"; 112 } 113 114 void RISCVTargetAsmStreamer::emitDirectiveOptionArch( 115 ArrayRef<RISCVOptionArchArg> Args) { 116 OS << "\t.option\tarch"; 117 for (const auto &Arg : Args) { 118 OS << ", "; 119 switch (Arg.Type) { 120 case RISCVOptionArchArgType::Full: 121 break; 122 case RISCVOptionArchArgType::Plus: 123 OS << "+"; 124 break; 125 case RISCVOptionArchArgType::Minus: 126 OS << "-"; 127 break; 128 } 129 OS << Arg.Value; 130 } 131 OS << "\n"; 132 } 133 134 void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) { 135 OS << "\t.variant_cc\t" << Symbol.getName() << "\n"; 136 } 137 138 void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) { 139 OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n"; 140 } 141 142 void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute, 143 StringRef String) { 144 OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n"; 145 } 146 147 void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute, 148 unsigned IntValue, 149 StringRef StringValue) {} 150 151 void RISCVTargetAsmStreamer::finishAttributeSection() {} 152