1 //===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides RISC-V specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVTargetStreamer.h" 14 #include "RISCVBaseInfo.h" 15 #include "RISCVMCTargetDesc.h" 16 #include "llvm/MC/MCSymbol.h" 17 #include "llvm/Support/FormattedStream.h" 18 #include "llvm/Support/RISCVAttributes.h" 19 #include "llvm/Support/RISCVISAInfo.h" 20 21 using namespace llvm; 22 23 RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} 24 25 void RISCVTargetStreamer::finish() { finishAttributeSection(); } 26 void RISCVTargetStreamer::reset() {} 27 28 void RISCVTargetStreamer::emitDirectiveOptionPush() {} 29 void RISCVTargetStreamer::emitDirectiveOptionPop() {} 30 void RISCVTargetStreamer::emitDirectiveOptionPIC() {} 31 void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {} 32 void RISCVTargetStreamer::emitDirectiveOptionRVC() {} 33 void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {} 34 void RISCVTargetStreamer::emitDirectiveOptionRelax() {} 35 void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {} 36 void RISCVTargetStreamer::emitDirectiveOptionArch( 37 ArrayRef<RISCVOptionArchArg> Args) {} 38 void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {} 39 void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {} 40 void RISCVTargetStreamer::finishAttributeSection() {} 41 void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute, 42 StringRef String) {} 43 void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute, 44 unsigned IntValue, 45 StringRef StringValue) {} 46 void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) { 47 assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI"); 48 TargetABI = ABI; 49 } 50 51 void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI, 52 bool EmitStackAlign) { 53 if (EmitStackAlign) { 54 if (TargetABI == RISCVABI::ABI_ILP32E) 55 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4); 56 else if (TargetABI == RISCVABI::ABI_LP64E) 57 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_8); 58 else 59 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16); 60 } 61 62 auto ParseResult = RISCVFeatures::parseFeatureBits( 63 STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits()); 64 if (!ParseResult) { 65 report_fatal_error(ParseResult.takeError()); 66 } else { 67 auto &ISAInfo = *ParseResult; 68 emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString()); 69 } 70 } 71 72 // This part is for ascii assembly output 73 RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S, 74 formatted_raw_ostream &OS) 75 : RISCVTargetStreamer(S), OS(OS) {} 76 77 void RISCVTargetAsmStreamer::emitDirectiveOptionPush() { 78 OS << "\t.option\tpush\n"; 79 } 80 81 void RISCVTargetAsmStreamer::emitDirectiveOptionPop() { 82 OS << "\t.option\tpop\n"; 83 } 84 85 void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() { 86 OS << "\t.option\tpic\n"; 87 } 88 89 void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() { 90 OS << "\t.option\tnopic\n"; 91 } 92 93 void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() { 94 OS << "\t.option\trvc\n"; 95 } 96 97 void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() { 98 OS << "\t.option\tnorvc\n"; 99 } 100 101 void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() { 102 OS << "\t.option\trelax\n"; 103 } 104 105 void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() { 106 OS << "\t.option\tnorelax\n"; 107 } 108 109 void RISCVTargetAsmStreamer::emitDirectiveOptionArch( 110 ArrayRef<RISCVOptionArchArg> Args) { 111 OS << "\t.option\tarch"; 112 for (const auto &Arg : Args) { 113 OS << ", "; 114 switch (Arg.Type) { 115 case RISCVOptionArchArgType::Full: 116 break; 117 case RISCVOptionArchArgType::Plus: 118 OS << "+"; 119 break; 120 case RISCVOptionArchArgType::Minus: 121 OS << "-"; 122 break; 123 } 124 OS << Arg.Value; 125 } 126 OS << "\n"; 127 } 128 129 void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) { 130 OS << "\t.variant_cc\t" << Symbol.getName() << "\n"; 131 } 132 133 void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) { 134 OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n"; 135 } 136 137 void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute, 138 StringRef String) { 139 OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n"; 140 } 141 142 void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute, 143 unsigned IntValue, 144 StringRef StringValue) {} 145 146 void RISCVTargetAsmStreamer::finishAttributeSection() {} 147