1 //===-- RISCVMCTargetDesc.cpp - RISC-V Target Descriptions ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// This file provides RISC-V specific target descriptions. 10 /// 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVMCTargetDesc.h" 14 #include "RISCVBaseInfo.h" 15 #include "RISCVELFStreamer.h" 16 #include "RISCVInstPrinter.h" 17 #include "RISCVMCAsmInfo.h" 18 #include "RISCVMCObjectFileInfo.h" 19 #include "RISCVTargetStreamer.h" 20 #include "TargetInfo/RISCVTargetInfo.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/MC/MCAsmBackend.h" 23 #include "llvm/MC/MCAsmInfo.h" 24 #include "llvm/MC/MCCodeEmitter.h" 25 #include "llvm/MC/MCInstrAnalysis.h" 26 #include "llvm/MC/MCInstrInfo.h" 27 #include "llvm/MC/MCObjectFileInfo.h" 28 #include "llvm/MC/MCObjectWriter.h" 29 #include "llvm/MC/MCRegisterInfo.h" 30 #include "llvm/MC/MCStreamer.h" 31 #include "llvm/MC/MCSubtargetInfo.h" 32 #include "llvm/MC/TargetRegistry.h" 33 #include "llvm/Support/ErrorHandling.h" 34 35 #define GET_INSTRINFO_MC_DESC 36 #define ENABLE_INSTR_PREDICATE_VERIFIER 37 #include "RISCVGenInstrInfo.inc" 38 39 #define GET_REGINFO_MC_DESC 40 #include "RISCVGenRegisterInfo.inc" 41 42 #define GET_SUBTARGETINFO_MC_DESC 43 #include "RISCVGenSubtargetInfo.inc" 44 45 using namespace llvm; 46 47 static MCInstrInfo *createRISCVMCInstrInfo() { 48 MCInstrInfo *X = new MCInstrInfo(); 49 InitRISCVMCInstrInfo(X); 50 return X; 51 } 52 53 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { 54 MCRegisterInfo *X = new MCRegisterInfo(); 55 InitRISCVMCRegisterInfo(X, RISCV::X1); 56 return X; 57 } 58 59 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, 60 const Triple &TT, 61 const MCTargetOptions &Options) { 62 MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); 63 64 MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true); 65 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); 66 MAI->addInitialFrameState(Inst); 67 68 return MAI; 69 } 70 71 static MCObjectFileInfo * 72 createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, 73 bool LargeCodeModel = false) { 74 MCObjectFileInfo *MOFI = new RISCVMCObjectFileInfo(); 75 MOFI->initMCObjectFileInfo(Ctx, PIC, LargeCodeModel); 76 return MOFI; 77 } 78 79 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, 80 StringRef CPU, StringRef FS) { 81 if (CPU.empty() || CPU == "generic") 82 CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; 83 84 return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 85 } 86 87 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T, 88 unsigned SyntaxVariant, 89 const MCAsmInfo &MAI, 90 const MCInstrInfo &MII, 91 const MCRegisterInfo &MRI) { 92 return new RISCVInstPrinter(MAI, MII, MRI); 93 } 94 95 static MCTargetStreamer * 96 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { 97 const Triple &TT = STI.getTargetTriple(); 98 if (TT.isOSBinFormatELF()) 99 return new RISCVTargetELFStreamer(S, STI); 100 return nullptr; 101 } 102 103 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S, 104 formatted_raw_ostream &OS, 105 MCInstPrinter *InstPrint, 106 bool isVerboseAsm) { 107 return new RISCVTargetAsmStreamer(S, OS); 108 } 109 110 static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) { 111 return new RISCVTargetStreamer(S); 112 } 113 114 namespace { 115 116 class RISCVMCInstrAnalysis : public MCInstrAnalysis { 117 public: 118 explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info) 119 : MCInstrAnalysis(Info) {} 120 121 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 122 uint64_t &Target) const override { 123 if (isConditionalBranch(Inst)) { 124 int64_t Imm; 125 if (Size == 2) 126 Imm = Inst.getOperand(1).getImm(); 127 else 128 Imm = Inst.getOperand(2).getImm(); 129 Target = Addr + Imm; 130 return true; 131 } 132 133 if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) { 134 Target = Addr + Inst.getOperand(0).getImm(); 135 return true; 136 } 137 138 if (Inst.getOpcode() == RISCV::JAL) { 139 Target = Addr + Inst.getOperand(1).getImm(); 140 return true; 141 } 142 143 return false; 144 } 145 146 bool isTerminator(const MCInst &Inst) const override { 147 if (MCInstrAnalysis::isTerminator(Inst)) 148 return true; 149 150 switch (Inst.getOpcode()) { 151 default: 152 return false; 153 case RISCV::JAL: 154 case RISCV::JALR: 155 return Inst.getOperand(0).getReg() == RISCV::X0; 156 } 157 } 158 159 bool isCall(const MCInst &Inst) const override { 160 if (MCInstrAnalysis::isCall(Inst)) 161 return true; 162 163 switch (Inst.getOpcode()) { 164 default: 165 return false; 166 case RISCV::JAL: 167 case RISCV::JALR: 168 return Inst.getOperand(0).getReg() != RISCV::X0; 169 } 170 } 171 172 bool isReturn(const MCInst &Inst) const override { 173 if (MCInstrAnalysis::isReturn(Inst)) 174 return true; 175 176 switch (Inst.getOpcode()) { 177 default: 178 return false; 179 case RISCV::JALR: 180 return Inst.getOperand(0).getReg() == RISCV::X0 && 181 maybeReturnAddress(Inst.getOperand(1).getReg()); 182 case RISCV::C_JR: 183 return maybeReturnAddress(Inst.getOperand(0).getReg()); 184 } 185 } 186 187 bool isBranch(const MCInst &Inst) const override { 188 if (MCInstrAnalysis::isBranch(Inst)) 189 return true; 190 191 return isBranchImpl(Inst); 192 } 193 194 bool isUnconditionalBranch(const MCInst &Inst) const override { 195 if (MCInstrAnalysis::isUnconditionalBranch(Inst)) 196 return true; 197 198 return isBranchImpl(Inst); 199 } 200 201 bool isIndirectBranch(const MCInst &Inst) const override { 202 if (MCInstrAnalysis::isIndirectBranch(Inst)) 203 return true; 204 205 switch (Inst.getOpcode()) { 206 default: 207 return false; 208 case RISCV::JALR: 209 return Inst.getOperand(0).getReg() == RISCV::X0 && 210 !maybeReturnAddress(Inst.getOperand(1).getReg()); 211 case RISCV::C_JR: 212 return !maybeReturnAddress(Inst.getOperand(0).getReg()); 213 } 214 } 215 216 private: 217 static bool maybeReturnAddress(unsigned Reg) { 218 // X1 is used for normal returns, X5 for returns from outlined functions. 219 return Reg == RISCV::X1 || Reg == RISCV::X5; 220 } 221 222 static bool isBranchImpl(const MCInst &Inst) { 223 switch (Inst.getOpcode()) { 224 default: 225 return false; 226 case RISCV::JAL: 227 return Inst.getOperand(0).getReg() == RISCV::X0; 228 case RISCV::JALR: 229 return Inst.getOperand(0).getReg() == RISCV::X0 && 230 !maybeReturnAddress(Inst.getOperand(1).getReg()); 231 case RISCV::C_JR: 232 return !maybeReturnAddress(Inst.getOperand(0).getReg()); 233 } 234 } 235 }; 236 237 } // end anonymous namespace 238 239 static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) { 240 return new RISCVMCInstrAnalysis(Info); 241 } 242 243 namespace { 244 MCStreamer *createRISCVELFStreamer(const Triple &T, MCContext &Context, 245 std::unique_ptr<MCAsmBackend> &&MAB, 246 std::unique_ptr<MCObjectWriter> &&MOW, 247 std::unique_ptr<MCCodeEmitter> &&MCE, 248 bool RelaxAll) { 249 return createRISCVELFStreamer(Context, std::move(MAB), std::move(MOW), 250 std::move(MCE), RelaxAll); 251 } 252 } // end anonymous namespace 253 254 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() { 255 for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) { 256 TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo); 257 TargetRegistry::RegisterMCObjectFileInfo(*T, createRISCVMCObjectFileInfo); 258 TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo); 259 TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo); 260 TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend); 261 TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter); 262 TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter); 263 TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo); 264 TargetRegistry::RegisterELFStreamer(*T, createRISCVELFStreamer); 265 TargetRegistry::RegisterObjectTargetStreamer( 266 *T, createRISCVObjectTargetStreamer); 267 TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis); 268 269 // Register the asm target streamer. 270 TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer); 271 // Register the null target streamer. 272 TargetRegistry::RegisterNullTargetStreamer(*T, 273 createRISCVNullTargetStreamer); 274 } 275 } 276