1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// This file provides RISCV-specific target descriptions. 10 /// 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVMCTargetDesc.h" 14 #include "RISCVBaseInfo.h" 15 #include "RISCVELFStreamer.h" 16 #include "RISCVInstPrinter.h" 17 #include "RISCVMCAsmInfo.h" 18 #include "RISCVMCObjectFileInfo.h" 19 #include "RISCVTargetStreamer.h" 20 #include "TargetInfo/RISCVTargetInfo.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/MC/MCAsmBackend.h" 23 #include "llvm/MC/MCAsmInfo.h" 24 #include "llvm/MC/MCCodeEmitter.h" 25 #include "llvm/MC/MCInstrAnalysis.h" 26 #include "llvm/MC/MCInstrInfo.h" 27 #include "llvm/MC/MCObjectFileInfo.h" 28 #include "llvm/MC/MCObjectWriter.h" 29 #include "llvm/MC/MCRegisterInfo.h" 30 #include "llvm/MC/MCStreamer.h" 31 #include "llvm/MC/MCSubtargetInfo.h" 32 #include "llvm/MC/TargetRegistry.h" 33 #include "llvm/Support/ErrorHandling.h" 34 35 #define GET_INSTRINFO_MC_DESC 36 #include "RISCVGenInstrInfo.inc" 37 38 #define GET_REGINFO_MC_DESC 39 #include "RISCVGenRegisterInfo.inc" 40 41 #define GET_SUBTARGETINFO_MC_DESC 42 #include "RISCVGenSubtargetInfo.inc" 43 44 using namespace llvm; 45 46 static MCInstrInfo *createRISCVMCInstrInfo() { 47 MCInstrInfo *X = new MCInstrInfo(); 48 InitRISCVMCInstrInfo(X); 49 return X; 50 } 51 52 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { 53 MCRegisterInfo *X = new MCRegisterInfo(); 54 InitRISCVMCRegisterInfo(X, RISCV::X1); 55 return X; 56 } 57 58 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, 59 const Triple &TT, 60 const MCTargetOptions &Options) { 61 MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); 62 63 MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true); 64 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); 65 MAI->addInitialFrameState(Inst); 66 67 return MAI; 68 } 69 70 static MCObjectFileInfo * 71 createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, 72 bool LargeCodeModel = false) { 73 MCObjectFileInfo *MOFI = new RISCVMCObjectFileInfo(); 74 MOFI->initMCObjectFileInfo(Ctx, PIC, LargeCodeModel); 75 return MOFI; 76 } 77 78 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, 79 StringRef CPU, StringRef FS) { 80 if (CPU.empty()) 81 CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; 82 if (CPU == "generic") 83 report_fatal_error(Twine("CPU 'generic' is not supported. Use ") + 84 (TT.isArch64Bit() ? "generic-rv64" : "generic-rv32")); 85 return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 86 } 87 88 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T, 89 unsigned SyntaxVariant, 90 const MCAsmInfo &MAI, 91 const MCInstrInfo &MII, 92 const MCRegisterInfo &MRI) { 93 return new RISCVInstPrinter(MAI, MII, MRI); 94 } 95 96 static MCTargetStreamer * 97 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { 98 const Triple &TT = STI.getTargetTriple(); 99 if (TT.isOSBinFormatELF()) 100 return new RISCVTargetELFStreamer(S, STI); 101 return nullptr; 102 } 103 104 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S, 105 formatted_raw_ostream &OS, 106 MCInstPrinter *InstPrint, 107 bool isVerboseAsm) { 108 return new RISCVTargetAsmStreamer(S, OS); 109 } 110 111 static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) { 112 return new RISCVTargetStreamer(S); 113 } 114 115 namespace { 116 117 class RISCVMCInstrAnalysis : public MCInstrAnalysis { 118 public: 119 explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info) 120 : MCInstrAnalysis(Info) {} 121 122 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 123 uint64_t &Target) const override { 124 if (isConditionalBranch(Inst)) { 125 int64_t Imm; 126 if (Size == 2) 127 Imm = Inst.getOperand(1).getImm(); 128 else 129 Imm = Inst.getOperand(2).getImm(); 130 Target = Addr + Imm; 131 return true; 132 } 133 134 if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) { 135 Target = Addr + Inst.getOperand(0).getImm(); 136 return true; 137 } 138 139 if (Inst.getOpcode() == RISCV::JAL) { 140 Target = Addr + Inst.getOperand(1).getImm(); 141 return true; 142 } 143 144 return false; 145 } 146 }; 147 148 } // end anonymous namespace 149 150 static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) { 151 return new RISCVMCInstrAnalysis(Info); 152 } 153 154 namespace { 155 MCStreamer *createRISCVELFStreamer(const Triple &T, MCContext &Context, 156 std::unique_ptr<MCAsmBackend> &&MAB, 157 std::unique_ptr<MCObjectWriter> &&MOW, 158 std::unique_ptr<MCCodeEmitter> &&MCE, 159 bool RelaxAll) { 160 return createRISCVELFStreamer(Context, std::move(MAB), std::move(MOW), 161 std::move(MCE), RelaxAll); 162 } 163 } // end anonymous namespace 164 165 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() { 166 for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) { 167 TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo); 168 TargetRegistry::RegisterMCObjectFileInfo(*T, createRISCVMCObjectFileInfo); 169 TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo); 170 TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo); 171 TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend); 172 TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter); 173 TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter); 174 TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo); 175 TargetRegistry::RegisterELFStreamer(*T, createRISCVELFStreamer); 176 TargetRegistry::RegisterObjectTargetStreamer( 177 *T, createRISCVObjectTargetStreamer); 178 TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis); 179 180 // Register the asm target streamer. 181 TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer); 182 // Register the null target streamer. 183 TargetRegistry::RegisterNullTargetStreamer(*T, 184 createRISCVNullTargetStreamer); 185 } 186 } 187