xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp (revision 0d8fe2373503aeac48492f28073049a8bfa4feb5)
1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This file provides RISCV-specific target descriptions.
10 ///
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVMCTargetDesc.h"
14 #include "RISCVBaseInfo.h"
15 #include "RISCVELFStreamer.h"
16 #include "RISCVInstPrinter.h"
17 #include "RISCVMCAsmInfo.h"
18 #include "RISCVTargetStreamer.h"
19 #include "TargetInfo/RISCVTargetInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCInstrAnalysis.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
29 
30 #define GET_INSTRINFO_MC_DESC
31 #include "RISCVGenInstrInfo.inc"
32 
33 #define GET_REGINFO_MC_DESC
34 #include "RISCVGenRegisterInfo.inc"
35 
36 #define GET_SUBTARGETINFO_MC_DESC
37 #include "RISCVGenSubtargetInfo.inc"
38 
39 using namespace llvm;
40 
41 static MCInstrInfo *createRISCVMCInstrInfo() {
42   MCInstrInfo *X = new MCInstrInfo();
43   InitRISCVMCInstrInfo(X);
44   return X;
45 }
46 
47 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
48   MCRegisterInfo *X = new MCRegisterInfo();
49   InitRISCVMCRegisterInfo(X, RISCV::X1);
50   return X;
51 }
52 
53 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
54                                        const Triple &TT,
55                                        const MCTargetOptions &Options) {
56   MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
57 
58   MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true);
59   MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
60   MAI->addInitialFrameState(Inst);
61 
62   return MAI;
63 }
64 
65 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
66                                                    StringRef CPU, StringRef FS) {
67   std::string CPUName = std::string(CPU);
68   if (CPUName.empty())
69     CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
70   return createRISCVMCSubtargetInfoImpl(TT, CPUName, /*TuneCPU*/ CPUName, FS);
71 }
72 
73 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
74                                                unsigned SyntaxVariant,
75                                                const MCAsmInfo &MAI,
76                                                const MCInstrInfo &MII,
77                                                const MCRegisterInfo &MRI) {
78   return new RISCVInstPrinter(MAI, MII, MRI);
79 }
80 
81 static MCTargetStreamer *
82 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
83   const Triple &TT = STI.getTargetTriple();
84   if (TT.isOSBinFormatELF())
85     return new RISCVTargetELFStreamer(S, STI);
86   return nullptr;
87 }
88 
89 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
90                                                       formatted_raw_ostream &OS,
91                                                       MCInstPrinter *InstPrint,
92                                                       bool isVerboseAsm) {
93   return new RISCVTargetAsmStreamer(S, OS);
94 }
95 
96 static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) {
97   return new RISCVTargetStreamer(S);
98 }
99 
100 namespace {
101 
102 class RISCVMCInstrAnalysis : public MCInstrAnalysis {
103 public:
104   explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
105       : MCInstrAnalysis(Info) {}
106 
107   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
108                       uint64_t &Target) const override {
109     if (isConditionalBranch(Inst)) {
110       int64_t Imm;
111       if (Size == 2)
112         Imm = Inst.getOperand(1).getImm();
113       else
114         Imm = Inst.getOperand(2).getImm();
115       Target = Addr + Imm;
116       return true;
117     }
118 
119     if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {
120       Target = Addr + Inst.getOperand(0).getImm();
121       return true;
122     }
123 
124     if (Inst.getOpcode() == RISCV::JAL) {
125       Target = Addr + Inst.getOperand(1).getImm();
126       return true;
127     }
128 
129     return false;
130   }
131 };
132 
133 } // end anonymous namespace
134 
135 static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
136   return new RISCVMCInstrAnalysis(Info);
137 }
138 
139 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
140   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
141     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
142     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
143     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
144     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
145     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
146     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
147     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
148     TargetRegistry::RegisterObjectTargetStreamer(
149         *T, createRISCVObjectTargetStreamer);
150     TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
151 
152     // Register the asm target streamer.
153     TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
154     // Register the null target streamer.
155     TargetRegistry::RegisterNullTargetStreamer(*T,
156                                                createRISCVNullTargetStreamer);
157   }
158 }
159