1 //===-- RISCVMCCodeEmitter.cpp - Convert RISC-V code to machine code ------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RISCVMCCodeEmitter class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/RISCVBaseInfo.h" 14 #include "MCTargetDesc/RISCVFixupKinds.h" 15 #include "MCTargetDesc/RISCVMCExpr.h" 16 #include "MCTargetDesc/RISCVMCTargetDesc.h" 17 #include "llvm/ADT/Statistic.h" 18 #include "llvm/MC/MCAsmInfo.h" 19 #include "llvm/MC/MCCodeEmitter.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstBuilder.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/MC/MCSymbol.h" 28 #include "llvm/Support/Casting.h" 29 #include "llvm/Support/EndianStream.h" 30 #include "llvm/Support/raw_ostream.h" 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mccodeemitter" 35 36 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 37 STATISTIC(MCNumFixups, "Number of MC fixups created"); 38 39 namespace { 40 class RISCVMCCodeEmitter : public MCCodeEmitter { 41 RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete; 42 void operator=(const RISCVMCCodeEmitter &) = delete; 43 MCContext &Ctx; 44 MCInstrInfo const &MCII; 45 46 public: 47 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) 48 : Ctx(ctx), MCII(MCII) {} 49 50 ~RISCVMCCodeEmitter() override = default; 51 52 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB, 53 SmallVectorImpl<MCFixup> &Fixups, 54 const MCSubtargetInfo &STI) const override; 55 56 void expandFunctionCall(const MCInst &MI, SmallVectorImpl<char> &CB, 57 SmallVectorImpl<MCFixup> &Fixups, 58 const MCSubtargetInfo &STI) const; 59 60 void expandAddTPRel(const MCInst &MI, SmallVectorImpl<char> &CB, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 64 void expandLongCondBr(const MCInst &MI, SmallVectorImpl<char> &CB, 65 SmallVectorImpl<MCFixup> &Fixups, 66 const MCSubtargetInfo &STI) const; 67 68 /// TableGen'erated function for getting the binary encoding for an 69 /// instruction. 70 uint64_t getBinaryCodeForInstr(const MCInst &MI, 71 SmallVectorImpl<MCFixup> &Fixups, 72 const MCSubtargetInfo &STI) const; 73 74 /// Return binary encoding of operand. If the machine operand requires 75 /// relocation, record the relocation and return zero. 76 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 77 SmallVectorImpl<MCFixup> &Fixups, 78 const MCSubtargetInfo &STI) const; 79 80 unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, 81 SmallVectorImpl<MCFixup> &Fixups, 82 const MCSubtargetInfo &STI) const; 83 84 unsigned getImmOpValue(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups, 86 const MCSubtargetInfo &STI) const; 87 88 unsigned getVMaskReg(const MCInst &MI, unsigned OpNo, 89 SmallVectorImpl<MCFixup> &Fixups, 90 const MCSubtargetInfo &STI) const; 91 92 unsigned getRlistOpValue(const MCInst &MI, unsigned OpNo, 93 SmallVectorImpl<MCFixup> &Fixups, 94 const MCSubtargetInfo &STI) const; 95 }; 96 } // end anonymous namespace 97 98 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII, 99 MCContext &Ctx) { 100 return new RISCVMCCodeEmitter(Ctx, MCII); 101 } 102 103 // Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with 104 // relocation types. We expand those pseudo-instructions while encoding them, 105 // meaning AUIPC and JALR won't go through RISC-V MC to MC compressed 106 // instruction transformation. This is acceptable because AUIPC has no 16-bit 107 // form and C_JALR has no immediate operand field. We let linker relaxation 108 // deal with it. When linker relaxation is enabled, AUIPC and JALR have a 109 // chance to relax to JAL. 110 // If the C extension is enabled, JAL has a chance relax to C_JAL. 111 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, 112 SmallVectorImpl<char> &CB, 113 SmallVectorImpl<MCFixup> &Fixups, 114 const MCSubtargetInfo &STI) const { 115 MCInst TmpInst; 116 MCOperand Func; 117 MCRegister Ra; 118 if (MI.getOpcode() == RISCV::PseudoTAIL) { 119 Func = MI.getOperand(0); 120 Ra = RISCV::X6; 121 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) { 122 Func = MI.getOperand(1); 123 Ra = MI.getOperand(0).getReg(); 124 } else if (MI.getOpcode() == RISCV::PseudoCALL) { 125 Func = MI.getOperand(0); 126 Ra = RISCV::X1; 127 } else if (MI.getOpcode() == RISCV::PseudoJump) { 128 Func = MI.getOperand(1); 129 Ra = MI.getOperand(0).getReg(); 130 } 131 uint32_t Binary; 132 133 assert(Func.isExpr() && "Expected expression"); 134 135 const MCExpr *CallExpr = Func.getExpr(); 136 137 // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type. 138 TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr); 139 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 140 support::endian::write(CB, Binary, support::little); 141 142 if (MI.getOpcode() == RISCV::PseudoTAIL || 143 MI.getOpcode() == RISCV::PseudoJump) 144 // Emit JALR X0, Ra, 0 145 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); 146 else 147 // Emit JALR Ra, Ra, 0 148 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); 149 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 150 support::endian::write(CB, Binary, support::little); 151 } 152 153 // Expand PseudoAddTPRel to a simple ADD with the correct relocation. 154 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, 155 SmallVectorImpl<char> &CB, 156 SmallVectorImpl<MCFixup> &Fixups, 157 const MCSubtargetInfo &STI) const { 158 MCOperand DestReg = MI.getOperand(0); 159 MCOperand SrcReg = MI.getOperand(1); 160 MCOperand TPReg = MI.getOperand(2); 161 assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 && 162 "Expected thread pointer as second input to TP-relative add"); 163 164 MCOperand SrcSymbol = MI.getOperand(3); 165 assert(SrcSymbol.isExpr() && 166 "Expected expression as third input to TP-relative add"); 167 168 const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr()); 169 assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD && 170 "Expected tprel_add relocation on TP-relative symbol"); 171 172 // Emit the correct tprel_add relocation for the symbol. 173 Fixups.push_back(MCFixup::create( 174 0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc())); 175 176 // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled. 177 if (STI.hasFeature(RISCV::FeatureRelax)) { 178 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); 179 Fixups.push_back(MCFixup::create( 180 0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc())); 181 } 182 183 // Emit a normal ADD instruction with the given operands. 184 MCInst TmpInst = MCInstBuilder(RISCV::ADD) 185 .addOperand(DestReg) 186 .addOperand(SrcReg) 187 .addOperand(TPReg); 188 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 189 support::endian::write(CB, Binary, support::little); 190 } 191 192 static unsigned getInvertedBranchOp(unsigned BrOp) { 193 switch (BrOp) { 194 default: 195 llvm_unreachable("Unexpected branch opcode!"); 196 case RISCV::PseudoLongBEQ: 197 return RISCV::BNE; 198 case RISCV::PseudoLongBNE: 199 return RISCV::BEQ; 200 case RISCV::PseudoLongBLT: 201 return RISCV::BGE; 202 case RISCV::PseudoLongBGE: 203 return RISCV::BLT; 204 case RISCV::PseudoLongBLTU: 205 return RISCV::BGEU; 206 case RISCV::PseudoLongBGEU: 207 return RISCV::BLTU; 208 } 209 } 210 211 // Expand PseudoLongBxx to an inverted conditional branch and an unconditional 212 // jump. 213 void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI, 214 SmallVectorImpl<char> &CB, 215 SmallVectorImpl<MCFixup> &Fixups, 216 const MCSubtargetInfo &STI) const { 217 MCRegister SrcReg1 = MI.getOperand(0).getReg(); 218 MCRegister SrcReg2 = MI.getOperand(1).getReg(); 219 MCOperand SrcSymbol = MI.getOperand(2); 220 unsigned Opcode = MI.getOpcode(); 221 bool IsEqTest = 222 Opcode == RISCV::PseudoLongBNE || Opcode == RISCV::PseudoLongBEQ; 223 224 bool UseCompressedBr = false; 225 if (IsEqTest && (STI.hasFeature(RISCV::FeatureStdExtC) || 226 STI.hasFeature(RISCV::FeatureStdExtZca))) { 227 if (RISCV::X8 <= SrcReg1.id() && SrcReg1.id() <= RISCV::X15 && 228 SrcReg2.id() == RISCV::X0) { 229 UseCompressedBr = true; 230 } else if (RISCV::X8 <= SrcReg2.id() && SrcReg2.id() <= RISCV::X15 && 231 SrcReg1.id() == RISCV::X0) { 232 std::swap(SrcReg1, SrcReg2); 233 UseCompressedBr = true; 234 } 235 } 236 237 uint32_t Offset; 238 if (UseCompressedBr) { 239 unsigned InvOpc = 240 Opcode == RISCV::PseudoLongBNE ? RISCV::C_BEQZ : RISCV::C_BNEZ; 241 MCInst TmpInst = MCInstBuilder(InvOpc).addReg(SrcReg1).addImm(6); 242 uint16_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 243 support::endian::write<uint16_t>(CB, Binary, support::little); 244 Offset = 2; 245 } else { 246 unsigned InvOpc = getInvertedBranchOp(Opcode); 247 MCInst TmpInst = 248 MCInstBuilder(InvOpc).addReg(SrcReg1).addReg(SrcReg2).addImm(8); 249 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 250 support::endian::write(CB, Binary, support::little); 251 Offset = 4; 252 } 253 254 // Emit an unconditional jump to the destination. 255 MCInst TmpInst = 256 MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addOperand(SrcSymbol); 257 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 258 support::endian::write(CB, Binary, support::little); 259 260 Fixups.clear(); 261 if (SrcSymbol.isExpr()) { 262 Fixups.push_back(MCFixup::create(Offset, SrcSymbol.getExpr(), 263 MCFixupKind(RISCV::fixup_riscv_jal), 264 MI.getLoc())); 265 } 266 } 267 268 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, 269 SmallVectorImpl<char> &CB, 270 SmallVectorImpl<MCFixup> &Fixups, 271 const MCSubtargetInfo &STI) const { 272 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 273 // Get byte count of instruction. 274 unsigned Size = Desc.getSize(); 275 276 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the 277 // expanded instructions for each pseudo is correct in the Size field of the 278 // tablegen definition for the pseudo. 279 switch (MI.getOpcode()) { 280 default: 281 break; 282 case RISCV::PseudoCALLReg: 283 case RISCV::PseudoCALL: 284 case RISCV::PseudoTAIL: 285 case RISCV::PseudoJump: 286 expandFunctionCall(MI, CB, Fixups, STI); 287 MCNumEmitted += 2; 288 return; 289 case RISCV::PseudoAddTPRel: 290 expandAddTPRel(MI, CB, Fixups, STI); 291 MCNumEmitted += 1; 292 return; 293 case RISCV::PseudoLongBEQ: 294 case RISCV::PseudoLongBNE: 295 case RISCV::PseudoLongBLT: 296 case RISCV::PseudoLongBGE: 297 case RISCV::PseudoLongBLTU: 298 case RISCV::PseudoLongBGEU: 299 expandLongCondBr(MI, CB, Fixups, STI); 300 MCNumEmitted += 2; 301 return; 302 } 303 304 switch (Size) { 305 default: 306 llvm_unreachable("Unhandled encodeInstruction length!"); 307 case 2: { 308 uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 309 support::endian::write<uint16_t>(CB, Bits, support::little); 310 break; 311 } 312 case 4: { 313 uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 314 support::endian::write(CB, Bits, support::little); 315 break; 316 } 317 } 318 319 ++MCNumEmitted; // Keep track of the # of mi's emitted. 320 } 321 322 unsigned 323 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, 324 SmallVectorImpl<MCFixup> &Fixups, 325 const MCSubtargetInfo &STI) const { 326 327 if (MO.isReg()) 328 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 329 330 if (MO.isImm()) 331 return static_cast<unsigned>(MO.getImm()); 332 333 llvm_unreachable("Unhandled expression!"); 334 return 0; 335 } 336 337 unsigned 338 RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, 339 SmallVectorImpl<MCFixup> &Fixups, 340 const MCSubtargetInfo &STI) const { 341 const MCOperand &MO = MI.getOperand(OpNo); 342 343 if (MO.isImm()) { 344 unsigned Res = MO.getImm(); 345 assert((Res & 1) == 0 && "LSB is non-zero"); 346 return Res >> 1; 347 } 348 349 return getImmOpValue(MI, OpNo, Fixups, STI); 350 } 351 352 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, 353 SmallVectorImpl<MCFixup> &Fixups, 354 const MCSubtargetInfo &STI) const { 355 bool EnableRelax = STI.hasFeature(RISCV::FeatureRelax); 356 const MCOperand &MO = MI.getOperand(OpNo); 357 358 MCInstrDesc const &Desc = MCII.get(MI.getOpcode()); 359 unsigned MIFrm = RISCVII::getFormat(Desc.TSFlags); 360 361 // If the destination is an immediate, there is nothing to do. 362 if (MO.isImm()) 363 return MO.getImm(); 364 365 assert(MO.isExpr() && 366 "getImmOpValue expects only expressions or immediates"); 367 const MCExpr *Expr = MO.getExpr(); 368 MCExpr::ExprKind Kind = Expr->getKind(); 369 RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid; 370 bool RelaxCandidate = false; 371 if (Kind == MCExpr::Target) { 372 const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr); 373 374 switch (RVExpr->getKind()) { 375 case RISCVMCExpr::VK_RISCV_None: 376 case RISCVMCExpr::VK_RISCV_Invalid: 377 case RISCVMCExpr::VK_RISCV_32_PCREL: 378 llvm_unreachable("Unhandled fixup kind!"); 379 case RISCVMCExpr::VK_RISCV_TPREL_ADD: 380 // tprel_add is only used to indicate that a relocation should be emitted 381 // for an add instruction used in TP-relative addressing. It should not be 382 // expanded as if representing an actual instruction operand and so to 383 // encounter it here is an error. 384 llvm_unreachable( 385 "VK_RISCV_TPREL_ADD should not represent an instruction operand"); 386 case RISCVMCExpr::VK_RISCV_LO: 387 if (MIFrm == RISCVII::InstFormatI) 388 FixupKind = RISCV::fixup_riscv_lo12_i; 389 else if (MIFrm == RISCVII::InstFormatS) 390 FixupKind = RISCV::fixup_riscv_lo12_s; 391 else 392 llvm_unreachable("VK_RISCV_LO used with unexpected instruction format"); 393 RelaxCandidate = true; 394 break; 395 case RISCVMCExpr::VK_RISCV_HI: 396 FixupKind = RISCV::fixup_riscv_hi20; 397 RelaxCandidate = true; 398 break; 399 case RISCVMCExpr::VK_RISCV_PCREL_LO: 400 if (MIFrm == RISCVII::InstFormatI) 401 FixupKind = RISCV::fixup_riscv_pcrel_lo12_i; 402 else if (MIFrm == RISCVII::InstFormatS) 403 FixupKind = RISCV::fixup_riscv_pcrel_lo12_s; 404 else 405 llvm_unreachable( 406 "VK_RISCV_PCREL_LO used with unexpected instruction format"); 407 RelaxCandidate = true; 408 break; 409 case RISCVMCExpr::VK_RISCV_PCREL_HI: 410 FixupKind = RISCV::fixup_riscv_pcrel_hi20; 411 RelaxCandidate = true; 412 break; 413 case RISCVMCExpr::VK_RISCV_GOT_HI: 414 FixupKind = RISCV::fixup_riscv_got_hi20; 415 break; 416 case RISCVMCExpr::VK_RISCV_TPREL_LO: 417 if (MIFrm == RISCVII::InstFormatI) 418 FixupKind = RISCV::fixup_riscv_tprel_lo12_i; 419 else if (MIFrm == RISCVII::InstFormatS) 420 FixupKind = RISCV::fixup_riscv_tprel_lo12_s; 421 else 422 llvm_unreachable( 423 "VK_RISCV_TPREL_LO used with unexpected instruction format"); 424 RelaxCandidate = true; 425 break; 426 case RISCVMCExpr::VK_RISCV_TPREL_HI: 427 FixupKind = RISCV::fixup_riscv_tprel_hi20; 428 RelaxCandidate = true; 429 break; 430 case RISCVMCExpr::VK_RISCV_TLS_GOT_HI: 431 FixupKind = RISCV::fixup_riscv_tls_got_hi20; 432 break; 433 case RISCVMCExpr::VK_RISCV_TLS_GD_HI: 434 FixupKind = RISCV::fixup_riscv_tls_gd_hi20; 435 break; 436 case RISCVMCExpr::VK_RISCV_CALL: 437 FixupKind = RISCV::fixup_riscv_call; 438 RelaxCandidate = true; 439 break; 440 case RISCVMCExpr::VK_RISCV_CALL_PLT: 441 FixupKind = RISCV::fixup_riscv_call_plt; 442 RelaxCandidate = true; 443 break; 444 } 445 } else if (Kind == MCExpr::SymbolRef && 446 cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) { 447 if (MIFrm == RISCVII::InstFormatJ) { 448 FixupKind = RISCV::fixup_riscv_jal; 449 } else if (MIFrm == RISCVII::InstFormatB) { 450 FixupKind = RISCV::fixup_riscv_branch; 451 } else if (MIFrm == RISCVII::InstFormatCJ) { 452 FixupKind = RISCV::fixup_riscv_rvc_jump; 453 } else if (MIFrm == RISCVII::InstFormatCB) { 454 FixupKind = RISCV::fixup_riscv_rvc_branch; 455 } else if (MIFrm == RISCVII::InstFormatI) { 456 FixupKind = RISCV::fixup_riscv_12_i; 457 } 458 } 459 460 assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!"); 461 462 Fixups.push_back( 463 MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc())); 464 ++MCNumFixups; 465 466 // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is 467 // enabled and the current fixup will result in a relocation that may be 468 // relaxed. 469 if (EnableRelax && RelaxCandidate) { 470 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); 471 Fixups.push_back( 472 MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), 473 MI.getLoc())); 474 ++MCNumFixups; 475 } 476 477 return 0; 478 } 479 480 unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, 481 SmallVectorImpl<MCFixup> &Fixups, 482 const MCSubtargetInfo &STI) const { 483 MCOperand MO = MI.getOperand(OpNo); 484 assert(MO.isReg() && "Expected a register."); 485 486 switch (MO.getReg()) { 487 default: 488 llvm_unreachable("Invalid mask register."); 489 case RISCV::V0: 490 return 0; 491 case RISCV::NoRegister: 492 return 1; 493 } 494 } 495 496 unsigned RISCVMCCodeEmitter::getRlistOpValue(const MCInst &MI, unsigned OpNo, 497 SmallVectorImpl<MCFixup> &Fixups, 498 const MCSubtargetInfo &STI) const { 499 const MCOperand &MO = MI.getOperand(OpNo); 500 assert(MO.isImm() && "Rlist operand must be immediate"); 501 auto Imm = MO.getImm(); 502 assert(Imm >= 4 && "EABI is currently not implemented"); 503 return Imm; 504 } 505 506 #include "RISCVGenMCCodeEmitter.inc" 507