1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RISCVMCCodeEmitter class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/RISCVFixupKinds.h" 14 #include "MCTargetDesc/RISCVMCExpr.h" 15 #include "MCTargetDesc/RISCVMCTargetDesc.h" 16 #include "Utils/RISCVBaseInfo.h" 17 #include "llvm/ADT/Statistic.h" 18 #include "llvm/MC/MCAsmInfo.h" 19 #include "llvm/MC/MCCodeEmitter.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstBuilder.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSymbol.h" 27 #include "llvm/Support/Casting.h" 28 #include "llvm/Support/EndianStream.h" 29 #include "llvm/Support/raw_ostream.h" 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "mccodeemitter" 34 35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 36 STATISTIC(MCNumFixups, "Number of MC fixups created"); 37 38 namespace { 39 class RISCVMCCodeEmitter : public MCCodeEmitter { 40 RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete; 41 void operator=(const RISCVMCCodeEmitter &) = delete; 42 MCContext &Ctx; 43 MCInstrInfo const &MCII; 44 45 public: 46 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) 47 : Ctx(ctx), MCII(MCII) {} 48 49 ~RISCVMCCodeEmitter() override {} 50 51 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 52 SmallVectorImpl<MCFixup> &Fixups, 53 const MCSubtargetInfo &STI) const override; 54 55 void expandFunctionCall(const MCInst &MI, raw_ostream &OS, 56 SmallVectorImpl<MCFixup> &Fixups, 57 const MCSubtargetInfo &STI) const; 58 59 void expandAddTPRel(const MCInst &MI, raw_ostream &OS, 60 SmallVectorImpl<MCFixup> &Fixups, 61 const MCSubtargetInfo &STI) const; 62 63 /// TableGen'erated function for getting the binary encoding for an 64 /// instruction. 65 uint64_t getBinaryCodeForInstr(const MCInst &MI, 66 SmallVectorImpl<MCFixup> &Fixups, 67 const MCSubtargetInfo &STI) const; 68 69 /// Return binary encoding of operand. If the machine operand requires 70 /// relocation, record the relocation and return zero. 71 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 72 SmallVectorImpl<MCFixup> &Fixups, 73 const MCSubtargetInfo &STI) const; 74 75 unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, 76 SmallVectorImpl<MCFixup> &Fixups, 77 const MCSubtargetInfo &STI) const; 78 79 unsigned getImmOpValue(const MCInst &MI, unsigned OpNo, 80 SmallVectorImpl<MCFixup> &Fixups, 81 const MCSubtargetInfo &STI) const; 82 }; 83 } // end anonymous namespace 84 85 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII, 86 const MCRegisterInfo &MRI, 87 MCContext &Ctx) { 88 return new RISCVMCCodeEmitter(Ctx, MCII); 89 } 90 91 // Expand PseudoCALL(Reg) and PseudoTAIL to AUIPC and JALR with relocation 92 // types. We expand PseudoCALL(Reg) and PseudoTAIL while encoding, meaning AUIPC 93 // and JALR won't go through RISCV MC to MC compressed instruction 94 // transformation. This is acceptable because AUIPC has no 16-bit form and 95 // C_JALR have no immediate operand field. We let linker relaxation deal with 96 // it. When linker relaxation enabled, AUIPC and JALR have chance relax to JAL. 97 // If C extension is enabled, JAL has chance relax to C_JAL. 98 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS, 99 SmallVectorImpl<MCFixup> &Fixups, 100 const MCSubtargetInfo &STI) const { 101 MCInst TmpInst; 102 MCOperand Func; 103 unsigned Ra; 104 if (MI.getOpcode() == RISCV::PseudoTAIL) { 105 Func = MI.getOperand(0); 106 Ra = RISCV::X6; 107 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) { 108 Func = MI.getOperand(1); 109 Ra = MI.getOperand(0).getReg(); 110 } else { 111 Func = MI.getOperand(0); 112 Ra = RISCV::X1; 113 } 114 uint32_t Binary; 115 116 assert(Func.isExpr() && "Expected expression"); 117 118 const MCExpr *CallExpr = Func.getExpr(); 119 120 // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type. 121 TmpInst = MCInstBuilder(RISCV::AUIPC) 122 .addReg(Ra) 123 .addOperand(MCOperand::createExpr(CallExpr)); 124 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 125 support::endian::write(OS, Binary, support::little); 126 127 if (MI.getOpcode() == RISCV::PseudoTAIL) 128 // Emit JALR X0, X6, 0 129 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); 130 else 131 // Emit JALR Ra, Ra, 0 132 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); 133 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 134 support::endian::write(OS, Binary, support::little); 135 } 136 137 // Expand PseudoAddTPRel to a simple ADD with the correct relocation. 138 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS, 139 SmallVectorImpl<MCFixup> &Fixups, 140 const MCSubtargetInfo &STI) const { 141 MCOperand DestReg = MI.getOperand(0); 142 MCOperand SrcReg = MI.getOperand(1); 143 MCOperand TPReg = MI.getOperand(2); 144 assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 && 145 "Expected thread pointer as second input to TP-relative add"); 146 147 MCOperand SrcSymbol = MI.getOperand(3); 148 assert(SrcSymbol.isExpr() && 149 "Expected expression as third input to TP-relative add"); 150 151 const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr()); 152 assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD && 153 "Expected tprel_add relocation on TP-relative symbol"); 154 155 // Emit the correct tprel_add relocation for the symbol. 156 Fixups.push_back(MCFixup::create( 157 0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc())); 158 159 // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled. 160 if (STI.getFeatureBits()[RISCV::FeatureRelax]) { 161 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); 162 Fixups.push_back(MCFixup::create( 163 0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc())); 164 } 165 166 // Emit a normal ADD instruction with the given operands. 167 MCInst TmpInst = MCInstBuilder(RISCV::ADD) 168 .addOperand(DestReg) 169 .addOperand(SrcReg) 170 .addOperand(TPReg); 171 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 172 support::endian::write(OS, Binary, support::little); 173 } 174 175 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 176 SmallVectorImpl<MCFixup> &Fixups, 177 const MCSubtargetInfo &STI) const { 178 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 179 // Get byte count of instruction. 180 unsigned Size = Desc.getSize(); 181 182 if (MI.getOpcode() == RISCV::PseudoCALLReg || 183 MI.getOpcode() == RISCV::PseudoCALL || 184 MI.getOpcode() == RISCV::PseudoTAIL) { 185 expandFunctionCall(MI, OS, Fixups, STI); 186 MCNumEmitted += 2; 187 return; 188 } 189 190 if (MI.getOpcode() == RISCV::PseudoAddTPRel) { 191 expandAddTPRel(MI, OS, Fixups, STI); 192 MCNumEmitted += 1; 193 return; 194 } 195 196 switch (Size) { 197 default: 198 llvm_unreachable("Unhandled encodeInstruction length!"); 199 case 2: { 200 uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 201 support::endian::write<uint16_t>(OS, Bits, support::little); 202 break; 203 } 204 case 4: { 205 uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 206 support::endian::write(OS, Bits, support::little); 207 break; 208 } 209 } 210 211 ++MCNumEmitted; // Keep track of the # of mi's emitted. 212 } 213 214 unsigned 215 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, 216 SmallVectorImpl<MCFixup> &Fixups, 217 const MCSubtargetInfo &STI) const { 218 219 if (MO.isReg()) 220 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 221 222 if (MO.isImm()) 223 return static_cast<unsigned>(MO.getImm()); 224 225 llvm_unreachable("Unhandled expression!"); 226 return 0; 227 } 228 229 unsigned 230 RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, 231 SmallVectorImpl<MCFixup> &Fixups, 232 const MCSubtargetInfo &STI) const { 233 const MCOperand &MO = MI.getOperand(OpNo); 234 235 if (MO.isImm()) { 236 unsigned Res = MO.getImm(); 237 assert((Res & 1) == 0 && "LSB is non-zero"); 238 return Res >> 1; 239 } 240 241 return getImmOpValue(MI, OpNo, Fixups, STI); 242 } 243 244 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, 245 SmallVectorImpl<MCFixup> &Fixups, 246 const MCSubtargetInfo &STI) const { 247 bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax]; 248 const MCOperand &MO = MI.getOperand(OpNo); 249 250 MCInstrDesc const &Desc = MCII.get(MI.getOpcode()); 251 unsigned MIFrm = Desc.TSFlags & RISCVII::InstFormatMask; 252 253 // If the destination is an immediate, there is nothing to do. 254 if (MO.isImm()) 255 return MO.getImm(); 256 257 assert(MO.isExpr() && 258 "getImmOpValue expects only expressions or immediates"); 259 const MCExpr *Expr = MO.getExpr(); 260 MCExpr::ExprKind Kind = Expr->getKind(); 261 RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid; 262 bool RelaxCandidate = false; 263 if (Kind == MCExpr::Target) { 264 const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr); 265 266 switch (RVExpr->getKind()) { 267 case RISCVMCExpr::VK_RISCV_None: 268 case RISCVMCExpr::VK_RISCV_Invalid: 269 case RISCVMCExpr::VK_RISCV_32_PCREL: 270 llvm_unreachable("Unhandled fixup kind!"); 271 case RISCVMCExpr::VK_RISCV_TPREL_ADD: 272 // tprel_add is only used to indicate that a relocation should be emitted 273 // for an add instruction used in TP-relative addressing. It should not be 274 // expanded as if representing an actual instruction operand and so to 275 // encounter it here is an error. 276 llvm_unreachable( 277 "VK_RISCV_TPREL_ADD should not represent an instruction operand"); 278 case RISCVMCExpr::VK_RISCV_LO: 279 if (MIFrm == RISCVII::InstFormatI) 280 FixupKind = RISCV::fixup_riscv_lo12_i; 281 else if (MIFrm == RISCVII::InstFormatS) 282 FixupKind = RISCV::fixup_riscv_lo12_s; 283 else 284 llvm_unreachable("VK_RISCV_LO used with unexpected instruction format"); 285 RelaxCandidate = true; 286 break; 287 case RISCVMCExpr::VK_RISCV_HI: 288 FixupKind = RISCV::fixup_riscv_hi20; 289 RelaxCandidate = true; 290 break; 291 case RISCVMCExpr::VK_RISCV_PCREL_LO: 292 if (MIFrm == RISCVII::InstFormatI) 293 FixupKind = RISCV::fixup_riscv_pcrel_lo12_i; 294 else if (MIFrm == RISCVII::InstFormatS) 295 FixupKind = RISCV::fixup_riscv_pcrel_lo12_s; 296 else 297 llvm_unreachable( 298 "VK_RISCV_PCREL_LO used with unexpected instruction format"); 299 RelaxCandidate = true; 300 break; 301 case RISCVMCExpr::VK_RISCV_PCREL_HI: 302 FixupKind = RISCV::fixup_riscv_pcrel_hi20; 303 RelaxCandidate = true; 304 break; 305 case RISCVMCExpr::VK_RISCV_GOT_HI: 306 FixupKind = RISCV::fixup_riscv_got_hi20; 307 break; 308 case RISCVMCExpr::VK_RISCV_TPREL_LO: 309 if (MIFrm == RISCVII::InstFormatI) 310 FixupKind = RISCV::fixup_riscv_tprel_lo12_i; 311 else if (MIFrm == RISCVII::InstFormatS) 312 FixupKind = RISCV::fixup_riscv_tprel_lo12_s; 313 else 314 llvm_unreachable( 315 "VK_RISCV_TPREL_LO used with unexpected instruction format"); 316 RelaxCandidate = true; 317 break; 318 case RISCVMCExpr::VK_RISCV_TPREL_HI: 319 FixupKind = RISCV::fixup_riscv_tprel_hi20; 320 RelaxCandidate = true; 321 break; 322 case RISCVMCExpr::VK_RISCV_TLS_GOT_HI: 323 FixupKind = RISCV::fixup_riscv_tls_got_hi20; 324 break; 325 case RISCVMCExpr::VK_RISCV_TLS_GD_HI: 326 FixupKind = RISCV::fixup_riscv_tls_gd_hi20; 327 break; 328 case RISCVMCExpr::VK_RISCV_CALL: 329 FixupKind = RISCV::fixup_riscv_call; 330 RelaxCandidate = true; 331 break; 332 case RISCVMCExpr::VK_RISCV_CALL_PLT: 333 FixupKind = RISCV::fixup_riscv_call_plt; 334 RelaxCandidate = true; 335 break; 336 } 337 } else if (Kind == MCExpr::SymbolRef && 338 cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) { 339 if (Desc.getOpcode() == RISCV::JAL) { 340 FixupKind = RISCV::fixup_riscv_jal; 341 } else if (MIFrm == RISCVII::InstFormatB) { 342 FixupKind = RISCV::fixup_riscv_branch; 343 } else if (MIFrm == RISCVII::InstFormatCJ) { 344 FixupKind = RISCV::fixup_riscv_rvc_jump; 345 } else if (MIFrm == RISCVII::InstFormatCB) { 346 FixupKind = RISCV::fixup_riscv_rvc_branch; 347 } 348 } 349 350 assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!"); 351 352 Fixups.push_back( 353 MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc())); 354 ++MCNumFixups; 355 356 // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is 357 // enabled and the current fixup will result in a relocation that may be 358 // relaxed. 359 if (EnableRelax && RelaxCandidate) { 360 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); 361 Fixups.push_back( 362 MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), 363 MI.getLoc())); 364 ++MCNumFixups; 365 } 366 367 return 0; 368 } 369 370 #include "RISCVGenMCCodeEmitter.inc" 371