1 //===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class prints an RISCV MCInst to a .s file. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVInstPrinter.h" 14 #include "RISCVBaseInfo.h" 15 #include "RISCVMCExpr.h" 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCRegisterInfo.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/MCSymbol.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/FormattedStream.h" 25 using namespace llvm; 26 27 #define DEBUG_TYPE "asm-printer" 28 29 // Include the auto-generated portion of the assembly writer. 30 #define PRINT_ALIAS_INSTR 31 #include "RISCVGenAsmWriter.inc" 32 33 static cl::opt<bool> 34 NoAliases("riscv-no-aliases", 35 cl::desc("Disable the emission of assembler pseudo instructions"), 36 cl::init(false), cl::Hidden); 37 38 // Print architectural register names rather than the ABI names (such as x2 39 // instead of sp). 40 // TODO: Make RISCVInstPrinter::getRegisterName non-static so that this can a 41 // member. 42 static bool ArchRegNames; 43 44 // The command-line flags above are used by llvm-mc and llc. They can be used by 45 // `llvm-objdump`, but we override their values here to handle options passed to 46 // `llvm-objdump` with `-M` (which matches GNU objdump). There did not seem to 47 // be an easier way to allow these options in all these tools, without doing it 48 // this way. 49 bool RISCVInstPrinter::applyTargetSpecificCLOption(StringRef Opt) { 50 if (Opt == "no-aliases") { 51 PrintAliases = false; 52 return true; 53 } 54 if (Opt == "numeric") { 55 ArchRegNames = true; 56 return true; 57 } 58 59 return false; 60 } 61 62 void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address, 63 StringRef Annot, const MCSubtargetInfo &STI, 64 raw_ostream &O) { 65 bool Res = false; 66 const MCInst *NewMI = MI; 67 MCInst UncompressedMI; 68 if (PrintAliases && !NoAliases) 69 Res = RISCVRVC::uncompress(UncompressedMI, *MI, STI); 70 if (Res) 71 NewMI = const_cast<MCInst *>(&UncompressedMI); 72 if (!PrintAliases || NoAliases || !printAliasInstr(NewMI, Address, STI, O)) 73 printInstruction(NewMI, Address, STI, O); 74 printAnnotation(O, Annot); 75 } 76 77 void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { 78 O << getRegisterName(Reg); 79 } 80 81 void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 82 const MCSubtargetInfo &STI, raw_ostream &O, 83 const char *Modifier) { 84 assert((Modifier == nullptr || Modifier[0] == 0) && "No modifiers supported"); 85 const MCOperand &MO = MI->getOperand(OpNo); 86 87 if (MO.isReg()) { 88 printRegName(O, MO.getReg()); 89 return; 90 } 91 92 if (MO.isImm()) { 93 O << MO.getImm(); 94 return; 95 } 96 97 assert(MO.isExpr() && "Unknown operand kind in printOperand"); 98 MO.getExpr()->print(O, &MAI); 99 } 100 101 void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address, 102 unsigned OpNo, 103 const MCSubtargetInfo &STI, 104 raw_ostream &O) { 105 const MCOperand &MO = MI->getOperand(OpNo); 106 if (!MO.isImm()) 107 return printOperand(MI, OpNo, STI, O); 108 109 if (PrintBranchImmAsAddress) { 110 uint64_t Target = Address + MO.getImm(); 111 if (!STI.hasFeature(RISCV::Feature64Bit)) 112 Target &= 0xffffffff; 113 O << formatHex(Target); 114 } else { 115 O << MO.getImm(); 116 } 117 } 118 119 void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo, 120 const MCSubtargetInfo &STI, 121 raw_ostream &O) { 122 unsigned Imm = MI->getOperand(OpNo).getImm(); 123 auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm); 124 if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits())) 125 O << SysReg->Name; 126 else 127 O << Imm; 128 } 129 130 void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo, 131 const MCSubtargetInfo &STI, 132 raw_ostream &O) { 133 unsigned FenceArg = MI->getOperand(OpNo).getImm(); 134 assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg"); 135 136 if ((FenceArg & RISCVFenceField::I) != 0) 137 O << 'i'; 138 if ((FenceArg & RISCVFenceField::O) != 0) 139 O << 'o'; 140 if ((FenceArg & RISCVFenceField::R) != 0) 141 O << 'r'; 142 if ((FenceArg & RISCVFenceField::W) != 0) 143 O << 'w'; 144 if (FenceArg == 0) 145 O << "0"; 146 } 147 148 void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo, 149 const MCSubtargetInfo &STI, raw_ostream &O) { 150 auto FRMArg = 151 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm()); 152 O << RISCVFPRndMode::roundingModeToString(FRMArg); 153 } 154 155 void RISCVInstPrinter::printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo, 156 const MCSubtargetInfo &STI, 157 raw_ostream &O) { 158 const MCOperand &MO = MI->getOperand(OpNo); 159 160 assert(MO.isReg() && "printZeroOffsetMemOp can only print register operands"); 161 O << "("; 162 printRegName(O, MO.getReg()); 163 O << ")"; 164 } 165 166 void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo, 167 const MCSubtargetInfo &STI, raw_ostream &O) { 168 unsigned Imm = MI->getOperand(OpNo).getImm(); 169 // Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx, 170 // or non-zero in bits 8 and above. 171 if (RISCVVType::getVLMUL(Imm) == RISCVII::VLMUL::LMUL_RESERVED || 172 RISCVVType::getSEW(Imm) > 64 || (Imm >> 8) != 0) { 173 O << Imm; 174 return; 175 } 176 // Print the text form. 177 RISCVVType::printVType(Imm, O); 178 } 179 180 void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo, 181 const MCSubtargetInfo &STI, 182 raw_ostream &O) { 183 const MCOperand &MO = MI->getOperand(OpNo); 184 185 assert(MO.isReg() && "printVMaskReg can only print register operands"); 186 if (MO.getReg() == RISCV::NoRegister) 187 return; 188 O << ", "; 189 printRegName(O, MO.getReg()); 190 O << ".t"; 191 } 192 193 const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) { 194 return getRegisterName(Reg, ArchRegNames ? RISCV::NoRegAltName 195 : RISCV::ABIRegAltName); 196 } 197