1 //===-- RISCVFixupKinds.h - RISCV Specific Fixup Entries --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H 10 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H 11 12 #include "llvm/MC/MCFixup.h" 13 #include <utility> 14 15 #undef RISCV 16 17 namespace llvm::RISCV { 18 enum Fixups { 19 // 20-bit fixup corresponding to %hi(foo) for instructions like lui 20 fixup_riscv_hi20 = FirstTargetFixupKind, 21 // 12-bit fixup corresponding to %lo(foo) for instructions like addi 22 fixup_riscv_lo12_i, 23 // 12-bit fixup corresponding to foo-bar for instructions like addi 24 fixup_riscv_12_i, 25 // 12-bit fixup corresponding to %lo(foo) for the S-type store instructions 26 fixup_riscv_lo12_s, 27 // 20-bit fixup corresponding to %pcrel_hi(foo) for instructions like auipc 28 fixup_riscv_pcrel_hi20, 29 // 12-bit fixup corresponding to %pcrel_lo(foo) for instructions like addi 30 fixup_riscv_pcrel_lo12_i, 31 // 12-bit fixup corresponding to %pcrel_lo(foo) for the S-type store 32 // instructions 33 fixup_riscv_pcrel_lo12_s, 34 // 20-bit fixup corresponding to %got_pcrel_hi(foo) for instructions like 35 // auipc 36 fixup_riscv_got_hi20, 37 // 20-bit fixup corresponding to %tprel_hi(foo) for instructions like lui 38 fixup_riscv_tprel_hi20, 39 // 12-bit fixup corresponding to %tprel_lo(foo) for instructions like addi 40 fixup_riscv_tprel_lo12_i, 41 // 12-bit fixup corresponding to %tprel_lo(foo) for the S-type store 42 // instructions 43 fixup_riscv_tprel_lo12_s, 44 // Fixup corresponding to %tprel_add(foo) for PseudoAddTPRel, used as a linker 45 // hint 46 fixup_riscv_tprel_add, 47 // 20-bit fixup corresponding to %tls_ie_pcrel_hi(foo) for instructions like 48 // auipc 49 fixup_riscv_tls_got_hi20, 50 // 20-bit fixup corresponding to %tls_gd_pcrel_hi(foo) for instructions like 51 // auipc 52 fixup_riscv_tls_gd_hi20, 53 // 20-bit fixup for symbol references in the jal instruction 54 fixup_riscv_jal, 55 // 12-bit fixup for symbol references in the branch instructions 56 fixup_riscv_branch, 57 // 11-bit fixup for symbol references in the compressed jump instruction 58 fixup_riscv_rvc_jump, 59 // 8-bit fixup for symbol references in the compressed branch instruction 60 fixup_riscv_rvc_branch, 61 // Fixup representing a legacy no-pic function call attached to the auipc 62 // instruction in a pair composed of adjacent auipc+jalr instructions. 63 fixup_riscv_call, 64 // Fixup representing a function call attached to the auipc instruction in a 65 // pair composed of adjacent auipc+jalr instructions. 66 fixup_riscv_call_plt, 67 // Used to generate an R_RISCV_RELAX relocation, which indicates the linker 68 // may relax the instruction pair. 69 fixup_riscv_relax, 70 // Used to generate an R_RISCV_ALIGN relocation, which indicates the linker 71 // should fixup the alignment after linker relaxation. 72 fixup_riscv_align, 73 // 8-bit fixup corresponding to R_RISCV_SET8 for local label assignment. 74 fixup_riscv_set_8, 75 // 8-bit fixup corresponding to R_RISCV_ADD8 for 8-bit symbolic difference 76 // paired relocations. 77 fixup_riscv_add_8, 78 // 8-bit fixup corresponding to R_RISCV_SUB8 for 8-bit symbolic difference 79 // paired relocations. 80 fixup_riscv_sub_8, 81 // 16-bit fixup corresponding to R_RISCV_SET16 for local label assignment. 82 fixup_riscv_set_16, 83 // 16-bit fixup corresponding to R_RISCV_ADD16 for 16-bit symbolic difference 84 // paired reloctions. 85 fixup_riscv_add_16, 86 // 16-bit fixup corresponding to R_RISCV_SUB16 for 16-bit symbolic difference 87 // paired reloctions. 88 fixup_riscv_sub_16, 89 // 32-bit fixup corresponding to R_RISCV_SET32 for local label assignment. 90 fixup_riscv_set_32, 91 // 32-bit fixup corresponding to R_RISCV_ADD32 for 32-bit symbolic difference 92 // paired relocations. 93 fixup_riscv_add_32, 94 // 32-bit fixup corresponding to R_RISCV_SUB32 for 32-bit symbolic difference 95 // paired relocations. 96 fixup_riscv_sub_32, 97 // 64-bit fixup corresponding to R_RISCV_ADD64 for 64-bit symbolic difference 98 // paired relocations. 99 fixup_riscv_add_64, 100 // 64-bit fixup corresponding to R_RISCV_SUB64 for 64-bit symbolic difference 101 // paired relocations. 102 fixup_riscv_sub_64, 103 // 6-bit fixup corresponding to R_RISCV_SET6 for local label assignment in 104 // DWARF CFA. 105 fixup_riscv_set_6b, 106 // 6-bit fixup corresponding to R_RISCV_SUB6 for local label assignment in 107 // DWARF CFA. 108 fixup_riscv_sub_6b, 109 110 // Used as a sentinel, must be the last 111 fixup_riscv_invalid, 112 NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind 113 }; 114 115 static inline std::pair<MCFixupKind, MCFixupKind> 116 getRelocPairForSize(unsigned Size) { 117 switch (Size) { 118 default: 119 llvm_unreachable("unsupported fixup size"); 120 case 1: 121 return std::make_pair(MCFixupKind(RISCV::fixup_riscv_add_8), 122 MCFixupKind(RISCV::fixup_riscv_sub_8)); 123 case 2: 124 return std::make_pair(MCFixupKind(RISCV::fixup_riscv_add_16), 125 MCFixupKind(RISCV::fixup_riscv_sub_16)); 126 case 4: 127 return std::make_pair(MCFixupKind(RISCV::fixup_riscv_add_32), 128 MCFixupKind(RISCV::fixup_riscv_sub_32)); 129 case 8: 130 return std::make_pair(MCFixupKind(RISCV::fixup_riscv_add_64), 131 MCFixupKind(RISCV::fixup_riscv_sub_64)); 132 } 133 } 134 135 } // end namespace llvm::RISCV 136 137 #endif 138