xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (revision ebacd8013fe5f7fdf9f6a5b286f6680dd2891036) 
1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15 
16 #include "MCTargetDesc/RISCVMCTargetDesc.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/SubtargetFeature.h"
21 #include "llvm/Support/RISCVISAInfo.h"
22 
23 namespace llvm {
24 
25 // RISCVII - This namespace holds all of the target specific flags that
26 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
27 namespace RISCVII {
28 enum {
29   InstFormatPseudo = 0,
30   InstFormatR = 1,
31   InstFormatR4 = 2,
32   InstFormatI = 3,
33   InstFormatS = 4,
34   InstFormatB = 5,
35   InstFormatU = 6,
36   InstFormatJ = 7,
37   InstFormatCR = 8,
38   InstFormatCI = 9,
39   InstFormatCSS = 10,
40   InstFormatCIW = 11,
41   InstFormatCL = 12,
42   InstFormatCS = 13,
43   InstFormatCA = 14,
44   InstFormatCB = 15,
45   InstFormatCJ = 16,
46   InstFormatOther = 17,
47 
48   InstFormatMask = 31,
49   InstFormatShift = 0,
50 
51   ConstraintShift = InstFormatShift + 5,
52   ConstraintMask = 0b111 << ConstraintShift,
53 
54   VLMulShift = ConstraintShift + 3,
55   VLMulMask = 0b111 << VLMulShift,
56 
57   // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst.
58   HasDummyMaskOpShift = VLMulShift + 3,
59   HasDummyMaskOpMask = 1 << HasDummyMaskOpShift,
60 
61   // Force a tail agnostic policy even this instruction has a tied destination.
62   ForceTailAgnosticShift = HasDummyMaskOpShift + 1,
63   ForceTailAgnosticMask = 1 << ForceTailAgnosticShift,
64 
65   // Does this instruction have a merge operand that must be removed when
66   // converting to MCInst. It will be the first explicit use operand. Used by
67   // RVV Pseudos.
68   HasMergeOpShift = ForceTailAgnosticShift + 1,
69   HasMergeOpMask = 1 << HasMergeOpShift,
70 
71   // Does this instruction have a SEW operand. It will be the last explicit
72   // operand unless there is a vector policy operand. Used by RVV Pseudos.
73   HasSEWOpShift = HasMergeOpShift + 1,
74   HasSEWOpMask = 1 << HasSEWOpShift,
75 
76   // Does this instruction have a VL operand. It will be the second to last
77   // explicit operand unless there is a vector policy operand. Used by RVV
78   // Pseudos.
79   HasVLOpShift = HasSEWOpShift + 1,
80   HasVLOpMask = 1 << HasVLOpShift,
81 
82   // Does this instruction have a vector policy operand. It will be the last
83   // explicit operand. Used by RVV Pseudos.
84   HasVecPolicyOpShift = HasVLOpShift + 1,
85   HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
86 
87   // Is this instruction a vector widening reduction instruction. Used by RVV
88   // Pseudos.
89   IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
90   IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
91 
92   // Does this instruction care about mask policy. If it is not, the mask policy
93   // could be either agnostic or undisturbed. For example, unmasked, store, and
94   // reduction operations result would not be affected by mask policy, so
95   // compiler has free to select either one.
96   UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
97   UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
98 };
99 
100 // Match with the definitions in RISCVInstrFormats.td
101 enum VConstraintType {
102   NoConstraint = 0,
103   VS2Constraint = 0b001,
104   VS1Constraint = 0b010,
105   VMConstraint = 0b100,
106 };
107 
108 enum VLMUL : uint8_t {
109   LMUL_1 = 0,
110   LMUL_2,
111   LMUL_4,
112   LMUL_8,
113   LMUL_RESERVED,
114   LMUL_F8,
115   LMUL_F4,
116   LMUL_F2
117 };
118 
119 enum {
120   TAIL_AGNOSTIC = 1,
121   MASK_AGNOSTIC = 2,
122 };
123 
124 // Helper functions to read TSFlags.
125 /// \returns the format of the instruction.
126 static inline unsigned getFormat(uint64_t TSFlags) {
127   return (TSFlags & InstFormatMask) >> InstFormatShift;
128 }
129 /// \returns the constraint for the instruction.
130 static inline VConstraintType getConstraint(uint64_t TSFlags) {
131   return static_cast<VConstraintType>((TSFlags & ConstraintMask) >>
132                                       ConstraintShift);
133 }
134 /// \returns the LMUL for the instruction.
135 static inline VLMUL getLMul(uint64_t TSFlags) {
136   return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
137 }
138 /// \returns true if there is a dummy mask operand for the instruction.
139 static inline bool hasDummyMaskOp(uint64_t TSFlags) {
140   return TSFlags & HasDummyMaskOpMask;
141 }
142 /// \returns true if tail agnostic is enforced for the instruction.
143 static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
144   return TSFlags & ForceTailAgnosticMask;
145 }
146 /// \returns true if there is a merge operand for the instruction.
147 static inline bool hasMergeOp(uint64_t TSFlags) {
148   return TSFlags & HasMergeOpMask;
149 }
150 /// \returns true if there is a SEW operand for the instruction.
151 static inline bool hasSEWOp(uint64_t TSFlags) {
152   return TSFlags & HasSEWOpMask;
153 }
154 /// \returns true if there is a VL operand for the instruction.
155 static inline bool hasVLOp(uint64_t TSFlags) {
156   return TSFlags & HasVLOpMask;
157 }
158 /// \returns true if there is a vector policy operand for this instruction.
159 static inline bool hasVecPolicyOp(uint64_t TSFlags) {
160   return TSFlags & HasVecPolicyOpMask;
161 }
162 /// \returns true if it is a vector widening reduction instruction.
163 static inline bool isRVVWideningReduction(uint64_t TSFlags) {
164   return TSFlags & IsRVVWideningReductionMask;
165 }
166 /// \returns true if mask policy is valid for the instruction.
167 static inline bool usesMaskPolicy(uint64_t TSFlags) {
168   return TSFlags & UsesMaskPolicyMask;
169 }
170 
171 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
172   const uint64_t TSFlags = Desc.TSFlags;
173   // This method is only called if we expect to have a VL operand, and all
174   // instructions with VL also have SEW.
175   assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
176   unsigned Offset = 2;
177   if (hasVecPolicyOp(TSFlags))
178     Offset = 3;
179   return Desc.getNumOperands() - Offset;
180 }
181 
182 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
183   const uint64_t TSFlags = Desc.TSFlags;
184   assert(hasSEWOp(TSFlags));
185   unsigned Offset = 1;
186   if (hasVecPolicyOp(TSFlags))
187     Offset = 2;
188   return Desc.getNumOperands() - Offset;
189 }
190 
191 // RISC-V Specific Machine Operand Flags
192 enum {
193   MO_None = 0,
194   MO_CALL = 1,
195   MO_PLT = 2,
196   MO_LO = 3,
197   MO_HI = 4,
198   MO_PCREL_LO = 5,
199   MO_PCREL_HI = 6,
200   MO_GOT_HI = 7,
201   MO_TPREL_LO = 8,
202   MO_TPREL_HI = 9,
203   MO_TPREL_ADD = 10,
204   MO_TLS_GOT_HI = 11,
205   MO_TLS_GD_HI = 12,
206 
207   // Used to differentiate between target-specific "direct" flags and "bitmask"
208   // flags. A machine operand can only have one "direct" flag, but can have
209   // multiple "bitmask" flags.
210   MO_DIRECT_FLAG_MASK = 15
211 };
212 } // namespace RISCVII
213 
214 namespace RISCVOp {
215 enum OperandType : unsigned {
216   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
217   OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
218   OPERAND_UIMM3,
219   OPERAND_UIMM4,
220   OPERAND_UIMM5,
221   OPERAND_UIMM7,
222   OPERAND_UIMM12,
223   OPERAND_SIMM12,
224   OPERAND_SIMM12_LSB00000,
225   OPERAND_UIMM20,
226   OPERAND_UIMMLOG2XLEN,
227   OPERAND_RVKRNUM,
228   OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM,
229   // Operand is either a register or uimm5, this is used by V extension pseudo
230   // instructions to represent a value that be passed as AVL to either vsetvli
231   // or vsetivli.
232   OPERAND_AVL,
233 };
234 } // namespace RISCVOp
235 
236 // Describes the predecessor/successor bits used in the FENCE instruction.
237 namespace RISCVFenceField {
238 enum FenceField {
239   I = 8,
240   O = 4,
241   R = 2,
242   W = 1
243 };
244 }
245 
246 // Describes the supported floating point rounding mode encodings.
247 namespace RISCVFPRndMode {
248 enum RoundingMode {
249   RNE = 0,
250   RTZ = 1,
251   RDN = 2,
252   RUP = 3,
253   RMM = 4,
254   DYN = 7,
255   Invalid
256 };
257 
258 inline static StringRef roundingModeToString(RoundingMode RndMode) {
259   switch (RndMode) {
260   default:
261     llvm_unreachable("Unknown floating point rounding mode");
262   case RISCVFPRndMode::RNE:
263     return "rne";
264   case RISCVFPRndMode::RTZ:
265     return "rtz";
266   case RISCVFPRndMode::RDN:
267     return "rdn";
268   case RISCVFPRndMode::RUP:
269     return "rup";
270   case RISCVFPRndMode::RMM:
271     return "rmm";
272   case RISCVFPRndMode::DYN:
273     return "dyn";
274   }
275 }
276 
277 inline static RoundingMode stringToRoundingMode(StringRef Str) {
278   return StringSwitch<RoundingMode>(Str)
279       .Case("rne", RISCVFPRndMode::RNE)
280       .Case("rtz", RISCVFPRndMode::RTZ)
281       .Case("rdn", RISCVFPRndMode::RDN)
282       .Case("rup", RISCVFPRndMode::RUP)
283       .Case("rmm", RISCVFPRndMode::RMM)
284       .Case("dyn", RISCVFPRndMode::DYN)
285       .Default(RISCVFPRndMode::Invalid);
286 }
287 
288 inline static bool isValidRoundingMode(unsigned Mode) {
289   switch (Mode) {
290   default:
291     return false;
292   case RISCVFPRndMode::RNE:
293   case RISCVFPRndMode::RTZ:
294   case RISCVFPRndMode::RDN:
295   case RISCVFPRndMode::RUP:
296   case RISCVFPRndMode::RMM:
297   case RISCVFPRndMode::DYN:
298     return true;
299   }
300 }
301 } // namespace RISCVFPRndMode
302 
303 namespace RISCVSysReg {
304 struct SysReg {
305   const char *Name;
306   const char *AltName;
307   const char *DeprecatedName;
308   unsigned Encoding;
309   // FIXME: add these additional fields when needed.
310   // Privilege Access: Read, Write, Read-Only.
311   // unsigned ReadWrite;
312   // Privilege Mode: User, System or Machine.
313   // unsigned Mode;
314   // Check field name.
315   // unsigned Extra;
316   // Register number without the privilege bits.
317   // unsigned Number;
318   FeatureBitset FeaturesRequired;
319   bool isRV32Only;
320 
321   bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
322     // Not in 32-bit mode.
323     if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
324       return false;
325     // No required feature associated with the system register.
326     if (FeaturesRequired.none())
327       return true;
328     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
329   }
330 };
331 
332 #define GET_SysRegsList_DECL
333 #include "RISCVGenSearchableTables.inc"
334 } // end namespace RISCVSysReg
335 
336 namespace RISCVInsnOpcode {
337 struct RISCVOpcode {
338   const char *Name;
339   unsigned Value;
340 };
341 
342 #define GET_RISCVOpcodesList_DECL
343 #include "RISCVGenSearchableTables.inc"
344 } // end namespace RISCVInsnOpcode
345 
346 namespace RISCVABI {
347 
348 enum ABI {
349   ABI_ILP32,
350   ABI_ILP32F,
351   ABI_ILP32D,
352   ABI_ILP32E,
353   ABI_LP64,
354   ABI_LP64F,
355   ABI_LP64D,
356   ABI_Unknown
357 };
358 
359 // Returns the target ABI, or else a StringError if the requested ABIName is
360 // not supported for the given TT and FeatureBits combination.
361 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
362                      StringRef ABIName);
363 
364 ABI getTargetABI(StringRef ABIName);
365 
366 // Returns the register used to hold the stack pointer after realignment.
367 MCRegister getBPReg();
368 
369 // Returns the register holding shadow call stack pointer.
370 MCRegister getSCSPReg();
371 
372 } // namespace RISCVABI
373 
374 namespace RISCVFeatures {
375 
376 // Validates if the given combination of features are valid for the target
377 // triple. Exits with report_fatal_error if not.
378 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
379 
380 llvm::Expected<std::unique_ptr<RISCVISAInfo>>
381 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
382 
383 } // namespace RISCVFeatures
384 
385 namespace RISCVVType {
386 // Is this a SEW value that can be encoded into the VTYPE format.
387 inline static bool isValidSEW(unsigned SEW) {
388   return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
389 }
390 
391 // Is this a LMUL value that can be encoded into the VTYPE format.
392 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
393   return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
394 }
395 
396 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
397                      bool MaskAgnostic);
398 
399 inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
400   unsigned VLMUL = VType & 0x7;
401   return static_cast<RISCVII::VLMUL>(VLMUL);
402 }
403 
404 // Decode VLMUL into 1,2,4,8 and fractional indicator.
405 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
406 
407 inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
408   assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
409   unsigned LmulLog2 = Log2_32(LMUL);
410   return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
411 }
412 
413 inline static unsigned decodeVSEW(unsigned VSEW) {
414   assert(VSEW < 8 && "Unexpected VSEW value");
415   return 1 << (VSEW + 3);
416 }
417 
418 inline static unsigned encodeSEW(unsigned SEW) {
419   assert(isValidSEW(SEW) && "Unexpected SEW value");
420   return Log2_32(SEW) - 3;
421 }
422 
423 inline static unsigned getSEW(unsigned VType) {
424   unsigned VSEW = (VType >> 3) & 0x7;
425   return decodeVSEW(VSEW);
426 }
427 
428 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
429 
430 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
431 
432 void printVType(unsigned VType, raw_ostream &OS);
433 
434 } // namespace RISCVVType
435 
436 } // namespace llvm
437 
438 #endif
439