1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone enum definitions for the RISCV target 10 // useful for the compiler back-end and the MC libraries. 11 // 12 //===----------------------------------------------------------------------===// 13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H 14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H 15 16 #include "MCTargetDesc/RISCVMCTargetDesc.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/SubtargetFeature.h" 21 22 namespace llvm { 23 24 // RISCVII - This namespace holds all of the target specific flags that 25 // instruction info tracks. All definitions must match RISCVInstrFormats.td. 26 namespace RISCVII { 27 enum { 28 InstFormatPseudo = 0, 29 InstFormatR = 1, 30 InstFormatR4 = 2, 31 InstFormatI = 3, 32 InstFormatS = 4, 33 InstFormatB = 5, 34 InstFormatU = 6, 35 InstFormatJ = 7, 36 InstFormatCR = 8, 37 InstFormatCI = 9, 38 InstFormatCSS = 10, 39 InstFormatCIW = 11, 40 InstFormatCL = 12, 41 InstFormatCS = 13, 42 InstFormatCA = 14, 43 InstFormatCB = 15, 44 InstFormatCJ = 16, 45 InstFormatOther = 17, 46 47 InstFormatMask = 31, 48 InstFormatShift = 0, 49 50 ConstraintShift = InstFormatShift + 5, 51 ConstraintMask = 0b111 << ConstraintShift, 52 53 VLMulShift = ConstraintShift + 3, 54 VLMulMask = 0b111 << VLMulShift, 55 56 // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst. 57 HasDummyMaskOpShift = VLMulShift + 3, 58 HasDummyMaskOpMask = 1 << HasDummyMaskOpShift, 59 60 // Force a tail agnostic policy even this instruction has a tied destination. 61 ForceTailAgnosticShift = HasDummyMaskOpShift + 1, 62 ForceTailAgnosticMask = 1 << ForceTailAgnosticShift, 63 64 // Does this instruction have a merge operand that must be removed when 65 // converting to MCInst. It will be the first explicit use operand. Used by 66 // RVV Pseudos. 67 HasMergeOpShift = ForceTailAgnosticShift + 1, 68 HasMergeOpMask = 1 << HasMergeOpShift, 69 70 // Does this instruction have a SEW operand. It will be the last explicit 71 // operand unless there is a vector policy operand. Used by RVV Pseudos. 72 HasSEWOpShift = HasMergeOpShift + 1, 73 HasSEWOpMask = 1 << HasSEWOpShift, 74 75 // Does this instruction have a VL operand. It will be the second to last 76 // explicit operand unless there is a vector policy operand. Used by RVV 77 // Pseudos. 78 HasVLOpShift = HasSEWOpShift + 1, 79 HasVLOpMask = 1 << HasVLOpShift, 80 81 // Does this instruction have a vector policy operand. It will be the last 82 // explicit operand. Used by RVV Pseudos. 83 HasVecPolicyOpShift = HasVLOpShift + 1, 84 HasVecPolicyOpMask = 1 << HasVecPolicyOpShift, 85 86 // Is this instruction a vector widening reduction instruction. Used by RVV 87 // Pseudos. 88 IsRVVWideningReductionShift = HasVecPolicyOpShift + 1, 89 IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift, 90 }; 91 92 // Match with the definitions in RISCVInstrFormatsV.td 93 enum VConstraintType { 94 NoConstraint = 0, 95 VS2Constraint = 0b001, 96 VS1Constraint = 0b010, 97 VMConstraint = 0b100, 98 }; 99 100 enum VLMUL : uint8_t { 101 LMUL_1 = 0, 102 LMUL_2, 103 LMUL_4, 104 LMUL_8, 105 LMUL_RESERVED, 106 LMUL_F8, 107 LMUL_F4, 108 LMUL_F2 109 }; 110 111 enum { 112 TAIL_UNDISTURBED = 0, 113 TAIL_AGNOSTIC = 1, 114 }; 115 116 // Helper functions to read TSFlags. 117 /// \returns the format of the instruction. 118 static inline unsigned getFormat(uint64_t TSFlags) { 119 return (TSFlags & InstFormatMask) >> InstFormatShift; 120 } 121 /// \returns the constraint for the instruction. 122 static inline VConstraintType getConstraint(uint64_t TSFlags) { 123 return static_cast<VConstraintType> 124 ((TSFlags & ConstraintMask) >> ConstraintShift); 125 } 126 /// \returns the LMUL for the instruction. 127 static inline VLMUL getLMul(uint64_t TSFlags) { 128 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift); 129 } 130 /// \returns true if there is a dummy mask operand for the instruction. 131 static inline bool hasDummyMaskOp(uint64_t TSFlags) { 132 return TSFlags & HasDummyMaskOpMask; 133 } 134 /// \returns true if tail agnostic is enforced for the instruction. 135 static inline bool doesForceTailAgnostic(uint64_t TSFlags) { 136 return TSFlags & ForceTailAgnosticMask; 137 } 138 /// \returns true if there is a merge operand for the instruction. 139 static inline bool hasMergeOp(uint64_t TSFlags) { 140 return TSFlags & HasMergeOpMask; 141 } 142 /// \returns true if there is a SEW operand for the instruction. 143 static inline bool hasSEWOp(uint64_t TSFlags) { 144 return TSFlags & HasSEWOpMask; 145 } 146 /// \returns true if there is a VL operand for the instruction. 147 static inline bool hasVLOp(uint64_t TSFlags) { 148 return TSFlags & HasVLOpMask; 149 } 150 /// \returns true if there is a vector policy operand for this instruction. 151 static inline bool hasVecPolicyOp(uint64_t TSFlags) { 152 return TSFlags & HasVecPolicyOpMask; 153 } 154 /// \returns true if it is a vector widening reduction instruction. 155 static inline bool isRVVWideningReduction(uint64_t TSFlags) { 156 return TSFlags & IsRVVWideningReductionMask; 157 } 158 159 // RISC-V Specific Machine Operand Flags 160 enum { 161 MO_None = 0, 162 MO_CALL = 1, 163 MO_PLT = 2, 164 MO_LO = 3, 165 MO_HI = 4, 166 MO_PCREL_LO = 5, 167 MO_PCREL_HI = 6, 168 MO_GOT_HI = 7, 169 MO_TPREL_LO = 8, 170 MO_TPREL_HI = 9, 171 MO_TPREL_ADD = 10, 172 MO_TLS_GOT_HI = 11, 173 MO_TLS_GD_HI = 12, 174 175 // Used to differentiate between target-specific "direct" flags and "bitmask" 176 // flags. A machine operand can only have one "direct" flag, but can have 177 // multiple "bitmask" flags. 178 MO_DIRECT_FLAG_MASK = 15 179 }; 180 } // namespace RISCVII 181 182 namespace RISCVOp { 183 enum OperandType : unsigned { 184 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET, 185 OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM, 186 OPERAND_UIMM3, 187 OPERAND_UIMM4, 188 OPERAND_UIMM5, 189 OPERAND_UIMM7, 190 OPERAND_UIMM12, 191 OPERAND_SIMM12, 192 OPERAND_UIMM20, 193 OPERAND_UIMMLOG2XLEN, 194 OPERAND_RVKRNUM, 195 OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM, 196 // Operand is either a register or uimm5, this is used by V extension pseudo 197 // instructions to represent a value that be passed as AVL to either vsetvli 198 // or vsetivli. 199 OPERAND_AVL, 200 }; 201 } // namespace RISCVOp 202 203 // Describes the predecessor/successor bits used in the FENCE instruction. 204 namespace RISCVFenceField { 205 enum FenceField { 206 I = 8, 207 O = 4, 208 R = 2, 209 W = 1 210 }; 211 } 212 213 // Describes the supported floating point rounding mode encodings. 214 namespace RISCVFPRndMode { 215 enum RoundingMode { 216 RNE = 0, 217 RTZ = 1, 218 RDN = 2, 219 RUP = 3, 220 RMM = 4, 221 DYN = 7, 222 Invalid 223 }; 224 225 inline static StringRef roundingModeToString(RoundingMode RndMode) { 226 switch (RndMode) { 227 default: 228 llvm_unreachable("Unknown floating point rounding mode"); 229 case RISCVFPRndMode::RNE: 230 return "rne"; 231 case RISCVFPRndMode::RTZ: 232 return "rtz"; 233 case RISCVFPRndMode::RDN: 234 return "rdn"; 235 case RISCVFPRndMode::RUP: 236 return "rup"; 237 case RISCVFPRndMode::RMM: 238 return "rmm"; 239 case RISCVFPRndMode::DYN: 240 return "dyn"; 241 } 242 } 243 244 inline static RoundingMode stringToRoundingMode(StringRef Str) { 245 return StringSwitch<RoundingMode>(Str) 246 .Case("rne", RISCVFPRndMode::RNE) 247 .Case("rtz", RISCVFPRndMode::RTZ) 248 .Case("rdn", RISCVFPRndMode::RDN) 249 .Case("rup", RISCVFPRndMode::RUP) 250 .Case("rmm", RISCVFPRndMode::RMM) 251 .Case("dyn", RISCVFPRndMode::DYN) 252 .Default(RISCVFPRndMode::Invalid); 253 } 254 255 inline static bool isValidRoundingMode(unsigned Mode) { 256 switch (Mode) { 257 default: 258 return false; 259 case RISCVFPRndMode::RNE: 260 case RISCVFPRndMode::RTZ: 261 case RISCVFPRndMode::RDN: 262 case RISCVFPRndMode::RUP: 263 case RISCVFPRndMode::RMM: 264 case RISCVFPRndMode::DYN: 265 return true; 266 } 267 } 268 } // namespace RISCVFPRndMode 269 270 namespace RISCVSysReg { 271 struct SysReg { 272 const char *Name; 273 const char *AltName; 274 const char *DeprecatedName; 275 unsigned Encoding; 276 // FIXME: add these additional fields when needed. 277 // Privilege Access: Read, Write, Read-Only. 278 // unsigned ReadWrite; 279 // Privilege Mode: User, System or Machine. 280 // unsigned Mode; 281 // Check field name. 282 // unsigned Extra; 283 // Register number without the privilege bits. 284 // unsigned Number; 285 FeatureBitset FeaturesRequired; 286 bool isRV32Only; 287 288 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const { 289 // Not in 32-bit mode. 290 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit]) 291 return false; 292 // No required feature associated with the system register. 293 if (FeaturesRequired.none()) 294 return true; 295 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; 296 } 297 }; 298 299 #define GET_SysRegsList_DECL 300 #include "RISCVGenSearchableTables.inc" 301 } // end namespace RISCVSysReg 302 303 namespace RISCVInsnOpcode { 304 struct RISCVOpcode { 305 const char *Name; 306 unsigned Value; 307 }; 308 309 #define GET_RISCVOpcodesList_DECL 310 #include "RISCVGenSearchableTables.inc" 311 } // end namespace RISCVInsnOpcode 312 313 namespace RISCVABI { 314 315 enum ABI { 316 ABI_ILP32, 317 ABI_ILP32F, 318 ABI_ILP32D, 319 ABI_ILP32E, 320 ABI_LP64, 321 ABI_LP64F, 322 ABI_LP64D, 323 ABI_Unknown 324 }; 325 326 // Returns the target ABI, or else a StringError if the requested ABIName is 327 // not supported for the given TT and FeatureBits combination. 328 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, 329 StringRef ABIName); 330 331 ABI getTargetABI(StringRef ABIName); 332 333 // Returns the register used to hold the stack pointer after realignment. 334 MCRegister getBPReg(); 335 336 // Returns the register holding shadow call stack pointer. 337 MCRegister getSCSPReg(); 338 339 } // namespace RISCVABI 340 341 namespace RISCVFeatures { 342 343 // Validates if the given combination of features are valid for the target 344 // triple. Exits with report_fatal_error if not. 345 void validate(const Triple &TT, const FeatureBitset &FeatureBits); 346 347 // Convert FeatureBitset to FeatureVector. 348 void toFeatureVector(std::vector<std::string> &FeatureVector, 349 const FeatureBitset &FeatureBits); 350 351 } // namespace RISCVFeatures 352 353 namespace RISCVVType { 354 // Is this a SEW value that can be encoded into the VTYPE format. 355 inline static bool isValidSEW(unsigned SEW) { 356 return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024; 357 } 358 359 // Is this a LMUL value that can be encoded into the VTYPE format. 360 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) { 361 return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1); 362 } 363 364 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, 365 bool MaskAgnostic); 366 367 inline static RISCVII::VLMUL getVLMUL(unsigned VType) { 368 unsigned VLMUL = VType & 0x7; 369 return static_cast<RISCVII::VLMUL>(VLMUL); 370 } 371 372 // Decode VLMUL into 1,2,4,8 and fractional indicator. 373 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL); 374 375 inline static unsigned decodeVSEW(unsigned VSEW) { 376 assert(VSEW < 8 && "Unexpected VSEW value"); 377 return 1 << (VSEW + 3); 378 } 379 380 inline static unsigned getSEW(unsigned VType) { 381 unsigned VSEW = (VType >> 3) & 0x7; 382 return decodeVSEW(VSEW); 383 } 384 385 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; } 386 387 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; } 388 389 void printVType(unsigned VType, raw_ostream &OS); 390 391 } // namespace RISCVVType 392 393 } // namespace llvm 394 395 #endif 396