xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (revision 5fb307d29b364982acbde82cbf77db3cae486f8c) 
1 //===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISC-V target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15 
16 #include "MCTargetDesc/RISCVMCTargetDesc.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/Support/RISCVISAInfo.h"
23 #include "llvm/TargetParser/SubtargetFeature.h"
24 
25 namespace llvm {
26 
27 // RISCVII - This namespace holds all of the target specific flags that
28 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
29 namespace RISCVII {
30 enum {
31   InstFormatPseudo = 0,
32   InstFormatR = 1,
33   InstFormatR4 = 2,
34   InstFormatI = 3,
35   InstFormatS = 4,
36   InstFormatB = 5,
37   InstFormatU = 6,
38   InstFormatJ = 7,
39   InstFormatCR = 8,
40   InstFormatCI = 9,
41   InstFormatCSS = 10,
42   InstFormatCIW = 11,
43   InstFormatCL = 12,
44   InstFormatCS = 13,
45   InstFormatCA = 14,
46   InstFormatCB = 15,
47   InstFormatCJ = 16,
48   InstFormatCU = 17,
49   InstFormatCLB = 18,
50   InstFormatCLH = 19,
51   InstFormatCSB = 20,
52   InstFormatCSH = 21,
53   InstFormatOther = 22,
54 
55   InstFormatMask = 31,
56   InstFormatShift = 0,
57 
58   ConstraintShift = InstFormatShift + 5,
59   VS2Constraint = 0b001 << ConstraintShift,
60   VS1Constraint = 0b010 << ConstraintShift,
61   VMConstraint = 0b100 << ConstraintShift,
62   ConstraintMask = 0b111 << ConstraintShift,
63 
64   VLMulShift = ConstraintShift + 3,
65   VLMulMask = 0b111 << VLMulShift,
66 
67   // Force a tail agnostic policy even this instruction has a tied destination.
68   ForceTailAgnosticShift = VLMulShift + 3,
69   ForceTailAgnosticMask = 1 << ForceTailAgnosticShift,
70 
71   // Is this a _TIED vector pseudo instruction. For these instructions we
72   // shouldn't skip the tied operand when converting to MC instructions.
73   IsTiedPseudoShift = ForceTailAgnosticShift + 1,
74   IsTiedPseudoMask = 1 << IsTiedPseudoShift,
75 
76   // Does this instruction have a SEW operand. It will be the last explicit
77   // operand unless there is a vector policy operand. Used by RVV Pseudos.
78   HasSEWOpShift = IsTiedPseudoShift + 1,
79   HasSEWOpMask = 1 << HasSEWOpShift,
80 
81   // Does this instruction have a VL operand. It will be the second to last
82   // explicit operand unless there is a vector policy operand. Used by RVV
83   // Pseudos.
84   HasVLOpShift = HasSEWOpShift + 1,
85   HasVLOpMask = 1 << HasVLOpShift,
86 
87   // Does this instruction have a vector policy operand. It will be the last
88   // explicit operand. Used by RVV Pseudos.
89   HasVecPolicyOpShift = HasVLOpShift + 1,
90   HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
91 
92   // Is this instruction a vector widening reduction instruction. Used by RVV
93   // Pseudos.
94   IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
95   IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
96 
97   // Does this instruction care about mask policy. If it is not, the mask policy
98   // could be either agnostic or undisturbed. For example, unmasked, store, and
99   // reduction operations result would not be affected by mask policy, so
100   // compiler has free to select either one.
101   UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
102   UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
103 
104   // Indicates that the result can be considered sign extended from bit 31. Some
105   // instructions with this flag aren't W instructions, but are either sign
106   // extended from a smaller size, always outputs a small integer, or put zeros
107   // in bits 63:31. Used by the SExtWRemoval pass.
108   IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
109   IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
110 
111   HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
112   HasRoundModeOpMask = 1 << HasRoundModeOpShift,
113 
114   UsesVXRMShift = HasRoundModeOpShift + 1,
115   UsesVXRMMask = 1 << UsesVXRMShift,
116 };
117 
118 enum VLMUL : uint8_t {
119   LMUL_1 = 0,
120   LMUL_2,
121   LMUL_4,
122   LMUL_8,
123   LMUL_RESERVED,
124   LMUL_F8,
125   LMUL_F4,
126   LMUL_F2
127 };
128 
129 enum {
130   TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
131   TAIL_AGNOSTIC = 1,
132   MASK_AGNOSTIC = 2,
133 };
134 
135 // Helper functions to read TSFlags.
136 /// \returns the format of the instruction.
137 static inline unsigned getFormat(uint64_t TSFlags) {
138   return (TSFlags & InstFormatMask) >> InstFormatShift;
139 }
140 /// \returns the LMUL for the instruction.
141 static inline VLMUL getLMul(uint64_t TSFlags) {
142   return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
143 }
144 /// \returns true if tail agnostic is enforced for the instruction.
145 static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
146   return TSFlags & ForceTailAgnosticMask;
147 }
148 /// \returns true if this a _TIED pseudo.
149 static inline bool isTiedPseudo(uint64_t TSFlags) {
150   return TSFlags & IsTiedPseudoMask;
151 }
152 /// \returns true if there is a SEW operand for the instruction.
153 static inline bool hasSEWOp(uint64_t TSFlags) {
154   return TSFlags & HasSEWOpMask;
155 }
156 /// \returns true if there is a VL operand for the instruction.
157 static inline bool hasVLOp(uint64_t TSFlags) {
158   return TSFlags & HasVLOpMask;
159 }
160 /// \returns true if there is a vector policy operand for this instruction.
161 static inline bool hasVecPolicyOp(uint64_t TSFlags) {
162   return TSFlags & HasVecPolicyOpMask;
163 }
164 /// \returns true if it is a vector widening reduction instruction.
165 static inline bool isRVVWideningReduction(uint64_t TSFlags) {
166   return TSFlags & IsRVVWideningReductionMask;
167 }
168 /// \returns true if mask policy is valid for the instruction.
169 static inline bool usesMaskPolicy(uint64_t TSFlags) {
170   return TSFlags & UsesMaskPolicyMask;
171 }
172 
173 /// \returns true if there is a rounding mode operand for this instruction
174 static inline bool hasRoundModeOp(uint64_t TSFlags) {
175   return TSFlags & HasRoundModeOpMask;
176 }
177 
178 /// \returns true if this instruction uses vxrm
179 static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
180 
181 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
182   const uint64_t TSFlags = Desc.TSFlags;
183   // This method is only called if we expect to have a VL operand, and all
184   // instructions with VL also have SEW.
185   assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
186   unsigned Offset = 2;
187   if (hasVecPolicyOp(TSFlags))
188     Offset = 3;
189   return Desc.getNumOperands() - Offset;
190 }
191 
192 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
193   const uint64_t TSFlags = Desc.TSFlags;
194   assert(hasSEWOp(TSFlags));
195   unsigned Offset = 1;
196   if (hasVecPolicyOp(TSFlags))
197     Offset = 2;
198   return Desc.getNumOperands() - Offset;
199 }
200 
201 static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
202   assert(hasVecPolicyOp(Desc.TSFlags));
203   return Desc.getNumOperands() - 1;
204 }
205 
206 // Is the first def operand tied to the first use operand. This is true for
207 // vector pseudo instructions that have a merge operand for tail/mask
208 // undisturbed. It's also true for vector FMA instructions where one of the
209 // operands is also the destination register.
210 static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
211   return Desc.getNumDefs() < Desc.getNumOperands() &&
212          Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;
213 }
214 
215 // RISC-V Specific Machine Operand Flags
216 enum {
217   MO_None = 0,
218   MO_CALL = 1,
219   MO_PLT = 2,
220   MO_LO = 3,
221   MO_HI = 4,
222   MO_PCREL_LO = 5,
223   MO_PCREL_HI = 6,
224   MO_GOT_HI = 7,
225   MO_TPREL_LO = 8,
226   MO_TPREL_HI = 9,
227   MO_TPREL_ADD = 10,
228   MO_TLS_GOT_HI = 11,
229   MO_TLS_GD_HI = 12,
230 
231   // Used to differentiate between target-specific "direct" flags and "bitmask"
232   // flags. A machine operand can only have one "direct" flag, but can have
233   // multiple "bitmask" flags.
234   MO_DIRECT_FLAG_MASK = 15
235 };
236 } // namespace RISCVII
237 
238 namespace RISCVOp {
239 enum OperandType : unsigned {
240   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
241   OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
242   OPERAND_UIMM2,
243   OPERAND_UIMM2_LSB0,
244   OPERAND_UIMM3,
245   OPERAND_UIMM4,
246   OPERAND_UIMM5,
247   OPERAND_UIMM6,
248   OPERAND_UIMM7,
249   OPERAND_UIMM7_LSB00,
250   OPERAND_UIMM8_LSB00,
251   OPERAND_UIMM8,
252   OPERAND_UIMM8_LSB000,
253   OPERAND_UIMM8_GE32,
254   OPERAND_UIMM9_LSB000,
255   OPERAND_UIMM10_LSB00_NONZERO,
256   OPERAND_UIMM12,
257   OPERAND_ZERO,
258   OPERAND_SIMM5,
259   OPERAND_SIMM5_PLUS1,
260   OPERAND_SIMM6,
261   OPERAND_SIMM6_NONZERO,
262   OPERAND_SIMM10_LSB0000_NONZERO,
263   OPERAND_SIMM12,
264   OPERAND_SIMM12_LSB00000,
265   OPERAND_UIMM20,
266   OPERAND_UIMMLOG2XLEN,
267   OPERAND_UIMMLOG2XLEN_NONZERO,
268   OPERAND_CLUI_IMM,
269   OPERAND_VTYPEI10,
270   OPERAND_VTYPEI11,
271   OPERAND_RVKRNUM,
272   OPERAND_RVKRNUM_0_7,
273   OPERAND_RVKRNUM_1_10,
274   OPERAND_RVKRNUM_2_14,
275   OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM_2_14,
276   // Operand is either a register or uimm5, this is used by V extension pseudo
277   // instructions to represent a value that be passed as AVL to either vsetvli
278   // or vsetivli.
279   OPERAND_AVL,
280 };
281 } // namespace RISCVOp
282 
283 // Describes the predecessor/successor bits used in the FENCE instruction.
284 namespace RISCVFenceField {
285 enum FenceField {
286   I = 8,
287   O = 4,
288   R = 2,
289   W = 1
290 };
291 }
292 
293 // Describes the supported floating point rounding mode encodings.
294 namespace RISCVFPRndMode {
295 enum RoundingMode {
296   RNE = 0,
297   RTZ = 1,
298   RDN = 2,
299   RUP = 3,
300   RMM = 4,
301   DYN = 7,
302   Invalid
303 };
304 
305 inline static StringRef roundingModeToString(RoundingMode RndMode) {
306   switch (RndMode) {
307   default:
308     llvm_unreachable("Unknown floating point rounding mode");
309   case RISCVFPRndMode::RNE:
310     return "rne";
311   case RISCVFPRndMode::RTZ:
312     return "rtz";
313   case RISCVFPRndMode::RDN:
314     return "rdn";
315   case RISCVFPRndMode::RUP:
316     return "rup";
317   case RISCVFPRndMode::RMM:
318     return "rmm";
319   case RISCVFPRndMode::DYN:
320     return "dyn";
321   }
322 }
323 
324 inline static RoundingMode stringToRoundingMode(StringRef Str) {
325   return StringSwitch<RoundingMode>(Str)
326       .Case("rne", RISCVFPRndMode::RNE)
327       .Case("rtz", RISCVFPRndMode::RTZ)
328       .Case("rdn", RISCVFPRndMode::RDN)
329       .Case("rup", RISCVFPRndMode::RUP)
330       .Case("rmm", RISCVFPRndMode::RMM)
331       .Case("dyn", RISCVFPRndMode::DYN)
332       .Default(RISCVFPRndMode::Invalid);
333 }
334 
335 inline static bool isValidRoundingMode(unsigned Mode) {
336   switch (Mode) {
337   default:
338     return false;
339   case RISCVFPRndMode::RNE:
340   case RISCVFPRndMode::RTZ:
341   case RISCVFPRndMode::RDN:
342   case RISCVFPRndMode::RUP:
343   case RISCVFPRndMode::RMM:
344   case RISCVFPRndMode::DYN:
345     return true;
346   }
347 }
348 } // namespace RISCVFPRndMode
349 
350 //===----------------------------------------------------------------------===//
351 // Floating-point Immediates
352 //
353 
354 namespace RISCVLoadFPImm {
355 float getFPImm(unsigned Imm);
356 
357 /// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
358 /// immediate value. If the value cannot be represented as a 5-bit binary
359 /// encoding, then return -1.
360 int getLoadFPImm(APFloat FPImm);
361 } // namespace RISCVLoadFPImm
362 
363 namespace RISCVSysReg {
364 struct SysReg {
365   const char *Name;
366   const char *DeprecatedName;
367   unsigned Encoding;
368   // FIXME: add these additional fields when needed.
369   // Privilege Access: Read, Write, Read-Only.
370   // unsigned ReadWrite;
371   // Privilege Mode: User, System or Machine.
372   // unsigned Mode;
373   // Check field name.
374   // unsigned Extra;
375   // Register number without the privilege bits.
376   // unsigned Number;
377   FeatureBitset FeaturesRequired;
378   bool isRV32Only;
379 
380   bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
381     // Not in 32-bit mode.
382     if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
383       return false;
384     // No required feature associated with the system register.
385     if (FeaturesRequired.none())
386       return true;
387     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
388   }
389 
390   bool haveVendorRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
391     // Not in 32-bit mode.
392     if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
393       return false;
394     // No required feature associated with the system register.
395     if (FeaturesRequired.none())
396       return false;
397     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
398   }
399 };
400 
401 struct SiFiveReg : SysReg {};
402 
403 #define GET_SysRegsList_DECL
404 #define GET_SiFiveRegsList_DECL
405 #include "RISCVGenSearchableTables.inc"
406 } // end namespace RISCVSysReg
407 
408 namespace RISCVInsnOpcode {
409 struct RISCVOpcode {
410   const char *Name;
411   unsigned Value;
412 };
413 
414 #define GET_RISCVOpcodesList_DECL
415 #include "RISCVGenSearchableTables.inc"
416 } // end namespace RISCVInsnOpcode
417 
418 namespace RISCVABI {
419 
420 enum ABI {
421   ABI_ILP32,
422   ABI_ILP32F,
423   ABI_ILP32D,
424   ABI_ILP32E,
425   ABI_LP64,
426   ABI_LP64F,
427   ABI_LP64D,
428   ABI_LP64E,
429   ABI_Unknown
430 };
431 
432 // Returns the target ABI, or else a StringError if the requested ABIName is
433 // not supported for the given TT and FeatureBits combination.
434 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
435                      StringRef ABIName);
436 
437 ABI getTargetABI(StringRef ABIName);
438 
439 // Returns the register used to hold the stack pointer after realignment.
440 MCRegister getBPReg();
441 
442 // Returns the register holding shadow call stack pointer.
443 MCRegister getSCSPReg();
444 
445 } // namespace RISCVABI
446 
447 namespace RISCVFeatures {
448 
449 // Validates if the given combination of features are valid for the target
450 // triple. Exits with report_fatal_error if not.
451 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
452 
453 llvm::Expected<std::unique_ptr<RISCVISAInfo>>
454 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
455 
456 } // namespace RISCVFeatures
457 
458 namespace RISCVVType {
459 // Is this a SEW value that can be encoded into the VTYPE format.
460 inline static bool isValidSEW(unsigned SEW) {
461   return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
462 }
463 
464 // Is this a LMUL value that can be encoded into the VTYPE format.
465 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
466   return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
467 }
468 
469 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
470                      bool MaskAgnostic);
471 
472 inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
473   unsigned VLMUL = VType & 0x7;
474   return static_cast<RISCVII::VLMUL>(VLMUL);
475 }
476 
477 // Decode VLMUL into 1,2,4,8 and fractional indicator.
478 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
479 
480 inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
481   assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
482   unsigned LmulLog2 = Log2_32(LMUL);
483   return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
484 }
485 
486 inline static unsigned decodeVSEW(unsigned VSEW) {
487   assert(VSEW < 8 && "Unexpected VSEW value");
488   return 1 << (VSEW + 3);
489 }
490 
491 inline static unsigned encodeSEW(unsigned SEW) {
492   assert(isValidSEW(SEW) && "Unexpected SEW value");
493   return Log2_32(SEW) - 3;
494 }
495 
496 inline static unsigned getSEW(unsigned VType) {
497   unsigned VSEW = (VType >> 3) & 0x7;
498   return decodeVSEW(VSEW);
499 }
500 
501 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
502 
503 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
504 
505 void printVType(unsigned VType, raw_ostream &OS);
506 
507 unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
508 
509 } // namespace RISCVVType
510 
511 namespace RISCVRVC {
512 bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
513 bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
514 } // namespace RISCVRVC
515 
516 namespace RISCVZC {
517 enum RLISTENCODE {
518   RA = 4,
519   RA_S0,
520   RA_S0_S1,
521   RA_S0_S2,
522   RA_S0_S3,
523   RA_S0_S4,
524   RA_S0_S5,
525   RA_S0_S6,
526   RA_S0_S7,
527   RA_S0_S8,
528   RA_S0_S9,
529   // note - to include s10, s11 must also be included
530   RA_S0_S11,
531   INVALID_RLIST,
532 };
533 
534 inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
535   assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
536   switch (EndReg) {
537   case RISCV::X1:
538     return RLISTENCODE::RA;
539   case RISCV::X8:
540     return RLISTENCODE::RA_S0;
541   case RISCV::X9:
542     return RLISTENCODE::RA_S0_S1;
543   case RISCV::X18:
544     return RLISTENCODE::RA_S0_S2;
545   case RISCV::X19:
546     return RLISTENCODE::RA_S0_S3;
547   case RISCV::X20:
548     return RLISTENCODE::RA_S0_S4;
549   case RISCV::X21:
550     return RLISTENCODE::RA_S0_S5;
551   case RISCV::X22:
552     return RLISTENCODE::RA_S0_S6;
553   case RISCV::X23:
554     return RLISTENCODE::RA_S0_S7;
555   case RISCV::X24:
556     return RLISTENCODE::RA_S0_S8;
557   case RISCV::X25:
558     return RLISTENCODE::RA_S0_S9;
559   case RISCV::X26:
560     return RLISTENCODE::INVALID_RLIST;
561   case RISCV::X27:
562     return RLISTENCODE::RA_S0_S11;
563   default:
564     llvm_unreachable("Undefined input.");
565   }
566 }
567 
568 inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64,
569                                        bool IsEABI) {
570   assert(RlistVal != RLISTENCODE::INVALID_RLIST &&
571          "{ra, s0-s10} is not supported, s11 must be included.");
572   if (IsEABI)
573     return 16;
574   if (!IsRV64) {
575     switch (RlistVal) {
576     case RLISTENCODE::RA:
577     case RLISTENCODE::RA_S0:
578     case RLISTENCODE::RA_S0_S1:
579     case RLISTENCODE::RA_S0_S2:
580       return 16;
581     case RLISTENCODE::RA_S0_S3:
582     case RLISTENCODE::RA_S0_S4:
583     case RLISTENCODE::RA_S0_S5:
584     case RLISTENCODE::RA_S0_S6:
585       return 32;
586     case RLISTENCODE::RA_S0_S7:
587     case RLISTENCODE::RA_S0_S8:
588     case RLISTENCODE::RA_S0_S9:
589       return 48;
590     case RLISTENCODE::RA_S0_S11:
591       return 64;
592     }
593   } else {
594     switch (RlistVal) {
595     case RLISTENCODE::RA:
596     case RLISTENCODE::RA_S0:
597       return 16;
598     case RLISTENCODE::RA_S0_S1:
599     case RLISTENCODE::RA_S0_S2:
600       return 32;
601     case RLISTENCODE::RA_S0_S3:
602     case RLISTENCODE::RA_S0_S4:
603       return 48;
604     case RLISTENCODE::RA_S0_S5:
605     case RLISTENCODE::RA_S0_S6:
606       return 64;
607     case RLISTENCODE::RA_S0_S7:
608     case RLISTENCODE::RA_S0_S8:
609       return 80;
610     case RLISTENCODE::RA_S0_S9:
611       return 96;
612     case RLISTENCODE::RA_S0_S11:
613       return 112;
614     }
615   }
616   llvm_unreachable("Unexpected RlistVal");
617 }
618 
619 inline static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal,
620                             int64_t StackAdjustment, bool IsRV64, bool IsEABI) {
621   if (RlistVal == RLISTENCODE::INVALID_RLIST)
622     return false;
623   unsigned stackAdj = getStackAdjBase(RlistVal, IsRV64, IsEABI);
624   SpimmVal = (StackAdjustment - stackAdj) / 16;
625   if (SpimmVal > 3)
626     return false;
627   return true;
628 }
629 
630 void printRlist(unsigned SlistEncode, raw_ostream &OS);
631 void printSpimm(int64_t Spimm, raw_ostream &OS);
632 } // namespace RISCVZC
633 
634 } // namespace llvm
635 
636 #endif
637