1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone enum definitions for the RISCV target 10 // useful for the compiler back-end and the MC libraries. 11 // 12 //===----------------------------------------------------------------------===// 13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H 14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H 15 16 #include "MCTargetDesc/RISCVMCTargetDesc.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/SubtargetFeature.h" 21 22 namespace llvm { 23 24 // RISCVII - This namespace holds all of the target specific flags that 25 // instruction info tracks. All definitions must match RISCVInstrFormats.td. 26 namespace RISCVII { 27 enum { 28 InstFormatPseudo = 0, 29 InstFormatR = 1, 30 InstFormatR4 = 2, 31 InstFormatI = 3, 32 InstFormatS = 4, 33 InstFormatB = 5, 34 InstFormatU = 6, 35 InstFormatJ = 7, 36 InstFormatCR = 8, 37 InstFormatCI = 9, 38 InstFormatCSS = 10, 39 InstFormatCIW = 11, 40 InstFormatCL = 12, 41 InstFormatCS = 13, 42 InstFormatCA = 14, 43 InstFormatCB = 15, 44 InstFormatCJ = 16, 45 InstFormatOther = 17, 46 47 InstFormatMask = 31, 48 InstFormatShift = 0, 49 50 ConstraintShift = InstFormatShift + 5, 51 ConstraintMask = 0b111 << ConstraintShift, 52 53 VLMulShift = ConstraintShift + 3, 54 VLMulMask = 0b111 << VLMulShift, 55 56 // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst. 57 HasDummyMaskOpShift = VLMulShift + 3, 58 HasDummyMaskOpMask = 1 << HasDummyMaskOpShift, 59 60 // Force a tail agnostic policy even this instruction has a tied destination. 61 ForceTailAgnosticShift = HasDummyMaskOpShift + 1, 62 ForceTailAgnosticMask = 1 << ForceTailAgnosticShift, 63 64 // Does this instruction have a merge operand that must be removed when 65 // converting to MCInst. It will be the first explicit use operand. Used by 66 // RVV Pseudos. 67 HasMergeOpShift = ForceTailAgnosticShift + 1, 68 HasMergeOpMask = 1 << HasMergeOpShift, 69 70 // Does this instruction have a SEW operand. It will be the last explicit 71 // operand unless there is a vector policy operand. Used by RVV Pseudos. 72 HasSEWOpShift = HasMergeOpShift + 1, 73 HasSEWOpMask = 1 << HasSEWOpShift, 74 75 // Does this instruction have a VL operand. It will be the second to last 76 // explicit operand unless there is a vector policy operand. Used by RVV 77 // Pseudos. 78 HasVLOpShift = HasSEWOpShift + 1, 79 HasVLOpMask = 1 << HasVLOpShift, 80 81 // Does this instruction have a vector policy operand. It will be the last 82 // explicit operand. Used by RVV Pseudos. 83 HasVecPolicyOpShift = HasVLOpShift + 1, 84 HasVecPolicyOpMask = 1 << HasVecPolicyOpShift, 85 86 // Is this instruction a vector widening reduction instruction. Used by RVV 87 // Pseudos. 88 IsRVVWideningReductionShift = HasVecPolicyOpShift + 1, 89 IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift, 90 }; 91 92 // Match with the definitions in RISCVInstrFormatsV.td 93 enum VConstraintType { 94 NoConstraint = 0, 95 VS2Constraint = 0b001, 96 VS1Constraint = 0b010, 97 VMConstraint = 0b100, 98 }; 99 100 enum VLMUL : uint8_t { 101 LMUL_1 = 0, 102 LMUL_2, 103 LMUL_4, 104 LMUL_8, 105 LMUL_RESERVED, 106 LMUL_F8, 107 LMUL_F4, 108 LMUL_F2 109 }; 110 111 enum { 112 TAIL_UNDISTURBED = 0, 113 TAIL_AGNOSTIC = 1, 114 }; 115 116 // Helper functions to read TSFlags. 117 /// \returns the format of the instruction. 118 static inline unsigned getFormat(uint64_t TSFlags) { 119 return (TSFlags & InstFormatMask) >> InstFormatShift; 120 } 121 /// \returns the constraint for the instruction. 122 static inline VConstraintType getConstraint(uint64_t TSFlags) { 123 return static_cast<VConstraintType> 124 ((TSFlags & ConstraintMask) >> ConstraintShift); 125 } 126 /// \returns the LMUL for the instruction. 127 static inline VLMUL getLMul(uint64_t TSFlags) { 128 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift); 129 } 130 /// \returns true if there is a dummy mask operand for the instruction. 131 static inline bool hasDummyMaskOp(uint64_t TSFlags) { 132 return TSFlags & HasDummyMaskOpMask; 133 } 134 /// \returns true if tail agnostic is enforced for the instruction. 135 static inline bool doesForceTailAgnostic(uint64_t TSFlags) { 136 return TSFlags & ForceTailAgnosticMask; 137 } 138 /// \returns true if there is a merge operand for the instruction. 139 static inline bool hasMergeOp(uint64_t TSFlags) { 140 return TSFlags & HasMergeOpMask; 141 } 142 /// \returns true if there is a SEW operand for the instruction. 143 static inline bool hasSEWOp(uint64_t TSFlags) { 144 return TSFlags & HasSEWOpMask; 145 } 146 /// \returns true if there is a VL operand for the instruction. 147 static inline bool hasVLOp(uint64_t TSFlags) { 148 return TSFlags & HasVLOpMask; 149 } 150 /// \returns true if there is a vector policy operand for this instruction. 151 static inline bool hasVecPolicyOp(uint64_t TSFlags) { 152 return TSFlags & HasVecPolicyOpMask; 153 } 154 /// \returns true if it is a vector widening reduction instruction. 155 static inline bool isRVVWideningReduction(uint64_t TSFlags) { 156 return TSFlags & IsRVVWideningReductionMask; 157 } 158 159 // RISC-V Specific Machine Operand Flags 160 enum { 161 MO_None = 0, 162 MO_CALL = 1, 163 MO_PLT = 2, 164 MO_LO = 3, 165 MO_HI = 4, 166 MO_PCREL_LO = 5, 167 MO_PCREL_HI = 6, 168 MO_GOT_HI = 7, 169 MO_TPREL_LO = 8, 170 MO_TPREL_HI = 9, 171 MO_TPREL_ADD = 10, 172 MO_TLS_GOT_HI = 11, 173 MO_TLS_GD_HI = 12, 174 175 // Used to differentiate between target-specific "direct" flags and "bitmask" 176 // flags. A machine operand can only have one "direct" flag, but can have 177 // multiple "bitmask" flags. 178 MO_DIRECT_FLAG_MASK = 15 179 }; 180 } // namespace RISCVII 181 182 namespace RISCVOp { 183 enum OperandType : unsigned { 184 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET, 185 OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM, 186 OPERAND_UIMM3, 187 OPERAND_UIMM4, 188 OPERAND_UIMM5, 189 OPERAND_UIMM7, 190 OPERAND_UIMM12, 191 OPERAND_SIMM12, 192 OPERAND_UIMM20, 193 OPERAND_UIMMLOG2XLEN, 194 OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN, 195 // Operand is either a register or uimm5, this is used by V extension pseudo 196 // instructions to represent a value that be passed as AVL to either vsetvli 197 // or vsetivli. 198 OPERAND_AVL, 199 }; 200 } // namespace RISCVOp 201 202 // Describes the predecessor/successor bits used in the FENCE instruction. 203 namespace RISCVFenceField { 204 enum FenceField { 205 I = 8, 206 O = 4, 207 R = 2, 208 W = 1 209 }; 210 } 211 212 // Describes the supported floating point rounding mode encodings. 213 namespace RISCVFPRndMode { 214 enum RoundingMode { 215 RNE = 0, 216 RTZ = 1, 217 RDN = 2, 218 RUP = 3, 219 RMM = 4, 220 DYN = 7, 221 Invalid 222 }; 223 224 inline static StringRef roundingModeToString(RoundingMode RndMode) { 225 switch (RndMode) { 226 default: 227 llvm_unreachable("Unknown floating point rounding mode"); 228 case RISCVFPRndMode::RNE: 229 return "rne"; 230 case RISCVFPRndMode::RTZ: 231 return "rtz"; 232 case RISCVFPRndMode::RDN: 233 return "rdn"; 234 case RISCVFPRndMode::RUP: 235 return "rup"; 236 case RISCVFPRndMode::RMM: 237 return "rmm"; 238 case RISCVFPRndMode::DYN: 239 return "dyn"; 240 } 241 } 242 243 inline static RoundingMode stringToRoundingMode(StringRef Str) { 244 return StringSwitch<RoundingMode>(Str) 245 .Case("rne", RISCVFPRndMode::RNE) 246 .Case("rtz", RISCVFPRndMode::RTZ) 247 .Case("rdn", RISCVFPRndMode::RDN) 248 .Case("rup", RISCVFPRndMode::RUP) 249 .Case("rmm", RISCVFPRndMode::RMM) 250 .Case("dyn", RISCVFPRndMode::DYN) 251 .Default(RISCVFPRndMode::Invalid); 252 } 253 254 inline static bool isValidRoundingMode(unsigned Mode) { 255 switch (Mode) { 256 default: 257 return false; 258 case RISCVFPRndMode::RNE: 259 case RISCVFPRndMode::RTZ: 260 case RISCVFPRndMode::RDN: 261 case RISCVFPRndMode::RUP: 262 case RISCVFPRndMode::RMM: 263 case RISCVFPRndMode::DYN: 264 return true; 265 } 266 } 267 } // namespace RISCVFPRndMode 268 269 namespace RISCVSysReg { 270 struct SysReg { 271 const char *Name; 272 const char *AltName; 273 const char *DeprecatedName; 274 unsigned Encoding; 275 // FIXME: add these additional fields when needed. 276 // Privilege Access: Read, Write, Read-Only. 277 // unsigned ReadWrite; 278 // Privilege Mode: User, System or Machine. 279 // unsigned Mode; 280 // Check field name. 281 // unsigned Extra; 282 // Register number without the privilege bits. 283 // unsigned Number; 284 FeatureBitset FeaturesRequired; 285 bool isRV32Only; 286 287 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const { 288 // Not in 32-bit mode. 289 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit]) 290 return false; 291 // No required feature associated with the system register. 292 if (FeaturesRequired.none()) 293 return true; 294 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; 295 } 296 }; 297 298 #define GET_SysRegsList_DECL 299 #include "RISCVGenSearchableTables.inc" 300 } // end namespace RISCVSysReg 301 302 namespace RISCVABI { 303 304 enum ABI { 305 ABI_ILP32, 306 ABI_ILP32F, 307 ABI_ILP32D, 308 ABI_ILP32E, 309 ABI_LP64, 310 ABI_LP64F, 311 ABI_LP64D, 312 ABI_Unknown 313 }; 314 315 // Returns the target ABI, or else a StringError if the requested ABIName is 316 // not supported for the given TT and FeatureBits combination. 317 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, 318 StringRef ABIName); 319 320 ABI getTargetABI(StringRef ABIName); 321 322 // Returns the register used to hold the stack pointer after realignment. 323 MCRegister getBPReg(); 324 325 // Returns the register holding shadow call stack pointer. 326 MCRegister getSCSPReg(); 327 328 } // namespace RISCVABI 329 330 namespace RISCVFeatures { 331 332 // Validates if the given combination of features are valid for the target 333 // triple. Exits with report_fatal_error if not. 334 void validate(const Triple &TT, const FeatureBitset &FeatureBits); 335 336 // Convert FeatureBitset to FeatureVector. 337 void toFeatureVector(std::vector<std::string> &FeatureVector, 338 const FeatureBitset &FeatureBits); 339 340 } // namespace RISCVFeatures 341 342 namespace RISCVVType { 343 // Is this a SEW value that can be encoded into the VTYPE format. 344 inline static bool isValidSEW(unsigned SEW) { 345 return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024; 346 } 347 348 // Is this a LMUL value that can be encoded into the VTYPE format. 349 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) { 350 return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1); 351 } 352 353 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, 354 bool MaskAgnostic); 355 356 inline static RISCVII::VLMUL getVLMUL(unsigned VType) { 357 unsigned VLMUL = VType & 0x7; 358 return static_cast<RISCVII::VLMUL>(VLMUL); 359 } 360 361 // Decode VLMUL into 1,2,4,8 and fractional indicator. 362 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL); 363 364 inline static unsigned decodeVSEW(unsigned VSEW) { 365 assert(VSEW < 8 && "Unexpected VSEW value"); 366 return 1 << (VSEW + 3); 367 } 368 369 inline static unsigned getSEW(unsigned VType) { 370 unsigned VSEW = (VType >> 3) & 0x7; 371 return decodeVSEW(VSEW); 372 } 373 374 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; } 375 376 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; } 377 378 void printVType(unsigned VType, raw_ostream &OS); 379 380 } // namespace RISCVVType 381 382 } // namespace llvm 383 384 #endif 385