xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (revision 258a0d760aa8b42899a000e30f610f900a402556) 
1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15 
16 #include "MCTargetDesc/RISCVMCTargetDesc.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/SubtargetFeature.h"
21 #include "llvm/Support/RISCVISAInfo.h"
22 
23 namespace llvm {
24 
25 // RISCVII - This namespace holds all of the target specific flags that
26 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
27 namespace RISCVII {
28 enum {
29   InstFormatPseudo = 0,
30   InstFormatR = 1,
31   InstFormatR4 = 2,
32   InstFormatI = 3,
33   InstFormatS = 4,
34   InstFormatB = 5,
35   InstFormatU = 6,
36   InstFormatJ = 7,
37   InstFormatCR = 8,
38   InstFormatCI = 9,
39   InstFormatCSS = 10,
40   InstFormatCIW = 11,
41   InstFormatCL = 12,
42   InstFormatCS = 13,
43   InstFormatCA = 14,
44   InstFormatCB = 15,
45   InstFormatCJ = 16,
46   InstFormatOther = 17,
47 
48   InstFormatMask = 31,
49   InstFormatShift = 0,
50 
51   ConstraintShift = InstFormatShift + 5,
52   ConstraintMask = 0b111 << ConstraintShift,
53 
54   VLMulShift = ConstraintShift + 3,
55   VLMulMask = 0b111 << VLMulShift,
56 
57   // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst.
58   HasDummyMaskOpShift = VLMulShift + 3,
59   HasDummyMaskOpMask = 1 << HasDummyMaskOpShift,
60 
61   // Force a tail agnostic policy even this instruction has a tied destination.
62   ForceTailAgnosticShift = HasDummyMaskOpShift + 1,
63   ForceTailAgnosticMask = 1 << ForceTailAgnosticShift,
64 
65   // Does this instruction have a merge operand that must be removed when
66   // converting to MCInst. It will be the first explicit use operand. Used by
67   // RVV Pseudos.
68   HasMergeOpShift = ForceTailAgnosticShift + 1,
69   HasMergeOpMask = 1 << HasMergeOpShift,
70 
71   // Does this instruction have a SEW operand. It will be the last explicit
72   // operand unless there is a vector policy operand. Used by RVV Pseudos.
73   HasSEWOpShift = HasMergeOpShift + 1,
74   HasSEWOpMask = 1 << HasSEWOpShift,
75 
76   // Does this instruction have a VL operand. It will be the second to last
77   // explicit operand unless there is a vector policy operand. Used by RVV
78   // Pseudos.
79   HasVLOpShift = HasSEWOpShift + 1,
80   HasVLOpMask = 1 << HasVLOpShift,
81 
82   // Does this instruction have a vector policy operand. It will be the last
83   // explicit operand. Used by RVV Pseudos.
84   HasVecPolicyOpShift = HasVLOpShift + 1,
85   HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
86 
87   // Is this instruction a vector widening reduction instruction. Used by RVV
88   // Pseudos.
89   IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
90   IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
91 
92   // Does this instruction care about mask policy. If it is not, the mask policy
93   // could be either agnostic or undisturbed. For example, unmasked, store, and
94   // reduction operations result would not be affected by mask policy, so
95   // compiler has free to select either one.
96   UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
97   UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
98 
99   // Indicates that the result can be considered sign extended from bit 31. Some
100   // instructions with this flag aren't W instructions, but are either sign
101   // extended from a smaller size, always outputs a small integer, or put zeros
102   // in bits 63:31. Used by the SExtWRemoval pass.
103   IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
104   IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
105 };
106 
107 // Match with the definitions in RISCVInstrFormats.td
108 enum VConstraintType {
109   NoConstraint = 0,
110   VS2Constraint = 0b001,
111   VS1Constraint = 0b010,
112   VMConstraint = 0b100,
113 };
114 
115 enum VLMUL : uint8_t {
116   LMUL_1 = 0,
117   LMUL_2,
118   LMUL_4,
119   LMUL_8,
120   LMUL_RESERVED,
121   LMUL_F8,
122   LMUL_F4,
123   LMUL_F2
124 };
125 
126 enum {
127   TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
128   TAIL_AGNOSTIC = 1,
129   MASK_AGNOSTIC = 2,
130 };
131 
132 // Helper functions to read TSFlags.
133 /// \returns the format of the instruction.
134 static inline unsigned getFormat(uint64_t TSFlags) {
135   return (TSFlags & InstFormatMask) >> InstFormatShift;
136 }
137 /// \returns the constraint for the instruction.
138 static inline VConstraintType getConstraint(uint64_t TSFlags) {
139   return static_cast<VConstraintType>((TSFlags & ConstraintMask) >>
140                                       ConstraintShift);
141 }
142 /// \returns the LMUL for the instruction.
143 static inline VLMUL getLMul(uint64_t TSFlags) {
144   return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
145 }
146 /// \returns true if there is a dummy mask operand for the instruction.
147 static inline bool hasDummyMaskOp(uint64_t TSFlags) {
148   return TSFlags & HasDummyMaskOpMask;
149 }
150 /// \returns true if tail agnostic is enforced for the instruction.
151 static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
152   return TSFlags & ForceTailAgnosticMask;
153 }
154 /// \returns true if there is a merge operand for the instruction.
155 static inline bool hasMergeOp(uint64_t TSFlags) {
156   return TSFlags & HasMergeOpMask;
157 }
158 /// \returns true if there is a SEW operand for the instruction.
159 static inline bool hasSEWOp(uint64_t TSFlags) {
160   return TSFlags & HasSEWOpMask;
161 }
162 /// \returns true if there is a VL operand for the instruction.
163 static inline bool hasVLOp(uint64_t TSFlags) {
164   return TSFlags & HasVLOpMask;
165 }
166 /// \returns true if there is a vector policy operand for this instruction.
167 static inline bool hasVecPolicyOp(uint64_t TSFlags) {
168   return TSFlags & HasVecPolicyOpMask;
169 }
170 /// \returns true if it is a vector widening reduction instruction.
171 static inline bool isRVVWideningReduction(uint64_t TSFlags) {
172   return TSFlags & IsRVVWideningReductionMask;
173 }
174 /// \returns true if mask policy is valid for the instruction.
175 static inline bool usesMaskPolicy(uint64_t TSFlags) {
176   return TSFlags & UsesMaskPolicyMask;
177 }
178 
179 static inline unsigned getMergeOpNum(const MCInstrDesc &Desc) {
180   assert(hasMergeOp(Desc.TSFlags));
181   assert(!Desc.isVariadic());
182   return Desc.getNumDefs();
183 }
184 
185 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
186   const uint64_t TSFlags = Desc.TSFlags;
187   // This method is only called if we expect to have a VL operand, and all
188   // instructions with VL also have SEW.
189   assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
190   unsigned Offset = 2;
191   if (hasVecPolicyOp(TSFlags))
192     Offset = 3;
193   return Desc.getNumOperands() - Offset;
194 }
195 
196 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
197   const uint64_t TSFlags = Desc.TSFlags;
198   assert(hasSEWOp(TSFlags));
199   unsigned Offset = 1;
200   if (hasVecPolicyOp(TSFlags))
201     Offset = 2;
202   return Desc.getNumOperands() - Offset;
203 }
204 
205 static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
206   assert(hasVecPolicyOp(Desc.TSFlags));
207   return Desc.getNumOperands() - 1;
208 }
209 
210 // RISC-V Specific Machine Operand Flags
211 enum {
212   MO_None = 0,
213   MO_CALL = 1,
214   MO_PLT = 2,
215   MO_LO = 3,
216   MO_HI = 4,
217   MO_PCREL_LO = 5,
218   MO_PCREL_HI = 6,
219   MO_GOT_HI = 7,
220   MO_TPREL_LO = 8,
221   MO_TPREL_HI = 9,
222   MO_TPREL_ADD = 10,
223   MO_TLS_GOT_HI = 11,
224   MO_TLS_GD_HI = 12,
225 
226   // Used to differentiate between target-specific "direct" flags and "bitmask"
227   // flags. A machine operand can only have one "direct" flag, but can have
228   // multiple "bitmask" flags.
229   MO_DIRECT_FLAG_MASK = 15
230 };
231 } // namespace RISCVII
232 
233 namespace RISCVOp {
234 enum OperandType : unsigned {
235   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
236   OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
237   OPERAND_UIMM3,
238   OPERAND_UIMM4,
239   OPERAND_UIMM5,
240   OPERAND_UIMM7,
241   OPERAND_UIMM7_LSB00,
242   OPERAND_UIMM8_LSB00,
243   OPERAND_UIMM8_LSB000,
244   OPERAND_UIMM12,
245   OPERAND_ZERO,
246   OPERAND_SIMM5,
247   OPERAND_SIMM5_PLUS1,
248   OPERAND_SIMM6,
249   OPERAND_SIMM6_NONZERO,
250   OPERAND_SIMM10_LSB0000_NONZERO,
251   OPERAND_SIMM12,
252   OPERAND_SIMM12_LSB00000,
253   OPERAND_UIMM20,
254   OPERAND_UIMMLOG2XLEN,
255   OPERAND_UIMMLOG2XLEN_NONZERO,
256   OPERAND_UIMM_SHFL,
257   OPERAND_VTYPEI10,
258   OPERAND_VTYPEI11,
259   OPERAND_RVKRNUM,
260   OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM,
261   // Operand is either a register or uimm5, this is used by V extension pseudo
262   // instructions to represent a value that be passed as AVL to either vsetvli
263   // or vsetivli.
264   OPERAND_AVL,
265 };
266 } // namespace RISCVOp
267 
268 // Describes the predecessor/successor bits used in the FENCE instruction.
269 namespace RISCVFenceField {
270 enum FenceField {
271   I = 8,
272   O = 4,
273   R = 2,
274   W = 1
275 };
276 }
277 
278 // Describes the supported floating point rounding mode encodings.
279 namespace RISCVFPRndMode {
280 enum RoundingMode {
281   RNE = 0,
282   RTZ = 1,
283   RDN = 2,
284   RUP = 3,
285   RMM = 4,
286   DYN = 7,
287   Invalid
288 };
289 
290 inline static StringRef roundingModeToString(RoundingMode RndMode) {
291   switch (RndMode) {
292   default:
293     llvm_unreachable("Unknown floating point rounding mode");
294   case RISCVFPRndMode::RNE:
295     return "rne";
296   case RISCVFPRndMode::RTZ:
297     return "rtz";
298   case RISCVFPRndMode::RDN:
299     return "rdn";
300   case RISCVFPRndMode::RUP:
301     return "rup";
302   case RISCVFPRndMode::RMM:
303     return "rmm";
304   case RISCVFPRndMode::DYN:
305     return "dyn";
306   }
307 }
308 
309 inline static RoundingMode stringToRoundingMode(StringRef Str) {
310   return StringSwitch<RoundingMode>(Str)
311       .Case("rne", RISCVFPRndMode::RNE)
312       .Case("rtz", RISCVFPRndMode::RTZ)
313       .Case("rdn", RISCVFPRndMode::RDN)
314       .Case("rup", RISCVFPRndMode::RUP)
315       .Case("rmm", RISCVFPRndMode::RMM)
316       .Case("dyn", RISCVFPRndMode::DYN)
317       .Default(RISCVFPRndMode::Invalid);
318 }
319 
320 inline static bool isValidRoundingMode(unsigned Mode) {
321   switch (Mode) {
322   default:
323     return false;
324   case RISCVFPRndMode::RNE:
325   case RISCVFPRndMode::RTZ:
326   case RISCVFPRndMode::RDN:
327   case RISCVFPRndMode::RUP:
328   case RISCVFPRndMode::RMM:
329   case RISCVFPRndMode::DYN:
330     return true;
331   }
332 }
333 } // namespace RISCVFPRndMode
334 
335 namespace RISCVSysReg {
336 struct SysReg {
337   const char *Name;
338   const char *AltName;
339   const char *DeprecatedName;
340   unsigned Encoding;
341   // FIXME: add these additional fields when needed.
342   // Privilege Access: Read, Write, Read-Only.
343   // unsigned ReadWrite;
344   // Privilege Mode: User, System or Machine.
345   // unsigned Mode;
346   // Check field name.
347   // unsigned Extra;
348   // Register number without the privilege bits.
349   // unsigned Number;
350   FeatureBitset FeaturesRequired;
351   bool isRV32Only;
352 
353   bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
354     // Not in 32-bit mode.
355     if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
356       return false;
357     // No required feature associated with the system register.
358     if (FeaturesRequired.none())
359       return true;
360     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
361   }
362 };
363 
364 #define GET_SysRegsList_DECL
365 #include "RISCVGenSearchableTables.inc"
366 } // end namespace RISCVSysReg
367 
368 namespace RISCVInsnOpcode {
369 struct RISCVOpcode {
370   const char *Name;
371   unsigned Value;
372 };
373 
374 #define GET_RISCVOpcodesList_DECL
375 #include "RISCVGenSearchableTables.inc"
376 } // end namespace RISCVInsnOpcode
377 
378 namespace RISCVABI {
379 
380 enum ABI {
381   ABI_ILP32,
382   ABI_ILP32F,
383   ABI_ILP32D,
384   ABI_ILP32E,
385   ABI_LP64,
386   ABI_LP64F,
387   ABI_LP64D,
388   ABI_Unknown
389 };
390 
391 // Returns the target ABI, or else a StringError if the requested ABIName is
392 // not supported for the given TT and FeatureBits combination.
393 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
394                      StringRef ABIName);
395 
396 ABI getTargetABI(StringRef ABIName);
397 
398 // Returns the register used to hold the stack pointer after realignment.
399 MCRegister getBPReg();
400 
401 // Returns the register holding shadow call stack pointer.
402 MCRegister getSCSPReg();
403 
404 } // namespace RISCVABI
405 
406 namespace RISCVFeatures {
407 
408 // Validates if the given combination of features are valid for the target
409 // triple. Exits with report_fatal_error if not.
410 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
411 
412 llvm::Expected<std::unique_ptr<RISCVISAInfo>>
413 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
414 
415 } // namespace RISCVFeatures
416 
417 namespace RISCVVType {
418 // Is this a SEW value that can be encoded into the VTYPE format.
419 inline static bool isValidSEW(unsigned SEW) {
420   return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
421 }
422 
423 // Is this a LMUL value that can be encoded into the VTYPE format.
424 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
425   return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
426 }
427 
428 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
429                      bool MaskAgnostic);
430 
431 inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
432   unsigned VLMUL = VType & 0x7;
433   return static_cast<RISCVII::VLMUL>(VLMUL);
434 }
435 
436 // Decode VLMUL into 1,2,4,8 and fractional indicator.
437 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
438 
439 inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
440   assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
441   unsigned LmulLog2 = Log2_32(LMUL);
442   return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
443 }
444 
445 inline static unsigned decodeVSEW(unsigned VSEW) {
446   assert(VSEW < 8 && "Unexpected VSEW value");
447   return 1 << (VSEW + 3);
448 }
449 
450 inline static unsigned encodeSEW(unsigned SEW) {
451   assert(isValidSEW(SEW) && "Unexpected SEW value");
452   return Log2_32(SEW) - 3;
453 }
454 
455 inline static unsigned getSEW(unsigned VType) {
456   unsigned VSEW = (VType >> 3) & 0x7;
457   return decodeVSEW(VSEW);
458 }
459 
460 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
461 
462 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
463 
464 void printVType(unsigned VType, raw_ostream &OS);
465 
466 unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
467 
468 } // namespace RISCVVType
469 
470 namespace RISCVRVC {
471 bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
472 bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
473 } // namespace RISCVRVC
474 
475 } // namespace llvm
476 
477 #endif
478