1 //===-- RISCVBaseInfo.cpp - Top level definitions for RISCV MC ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone enum definitions for the RISCV target 10 // useful for the compiler back-end and the MC libraries. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "RISCVBaseInfo.h" 15 #include "llvm/ADT/ArrayRef.h" 16 #include "llvm/ADT/Triple.h" 17 #include "llvm/MC/MCSubtargetInfo.h" 18 #include "llvm/Support/RISCVISAInfo.h" 19 #include "llvm/Support/raw_ostream.h" 20 21 namespace llvm { 22 23 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]; 24 25 namespace RISCVSysReg { 26 #define GET_SysRegsList_IMPL 27 #include "RISCVGenSearchableTables.inc" 28 } // namespace RISCVSysReg 29 30 namespace RISCVInsnOpcode { 31 #define GET_RISCVOpcodesList_IMPL 32 #include "RISCVGenSearchableTables.inc" 33 } // namespace RISCVInsnOpcode 34 35 namespace RISCVABI { 36 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, 37 StringRef ABIName) { 38 auto TargetABI = getTargetABI(ABIName); 39 bool IsRV64 = TT.isArch64Bit(); 40 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; 41 42 if (!ABIName.empty() && TargetABI == ABI_Unknown) { 43 errs() 44 << "'" << ABIName 45 << "' is not a recognized ABI for this target (ignoring target-abi)\n"; 46 } else if (ABIName.startswith("ilp32") && IsRV64) { 47 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring " 48 "target-abi)\n"; 49 TargetABI = ABI_Unknown; 50 } else if (ABIName.startswith("lp64") && !IsRV64) { 51 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring " 52 "target-abi)\n"; 53 TargetABI = ABI_Unknown; 54 } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) { 55 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser 56 errs() 57 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n"; 58 TargetABI = ABI_Unknown; 59 } 60 61 if (TargetABI != ABI_Unknown) 62 return TargetABI; 63 64 // For now, default to the ilp32/ilp32e/lp64 ABI if no explicit ABI is given 65 // or an invalid/unrecognised string is given. In the future, it might be 66 // worth changing this to default to ilp32f/lp64f and ilp32d/lp64d when 67 // hardware support for floating point is present. 68 if (IsRV32E) 69 return ABI_ILP32E; 70 if (IsRV64) 71 return ABI_LP64; 72 return ABI_ILP32; 73 } 74 75 ABI getTargetABI(StringRef ABIName) { 76 auto TargetABI = StringSwitch<ABI>(ABIName) 77 .Case("ilp32", ABI_ILP32) 78 .Case("ilp32f", ABI_ILP32F) 79 .Case("ilp32d", ABI_ILP32D) 80 .Case("ilp32e", ABI_ILP32E) 81 .Case("lp64", ABI_LP64) 82 .Case("lp64f", ABI_LP64F) 83 .Case("lp64d", ABI_LP64D) 84 .Default(ABI_Unknown); 85 return TargetABI; 86 } 87 88 // To avoid the BP value clobbered by a function call, we need to choose a 89 // callee saved register to save the value. RV32E only has X8 and X9 as callee 90 // saved registers and X8 will be used as fp. So we choose X9 as bp. 91 MCRegister getBPReg() { return RISCV::X9; } 92 93 // Returns the register holding shadow call stack pointer. 94 MCRegister getSCSPReg() { return RISCV::X18; } 95 96 } // namespace RISCVABI 97 98 namespace RISCVFeatures { 99 100 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { 101 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) 102 report_fatal_error("RV64 target requires an RV64 CPU"); 103 if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit]) 104 report_fatal_error("RV32 target requires an RV32 CPU"); 105 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) 106 report_fatal_error("RV32E can't be enabled for an RV64 target"); 107 } 108 109 void toFeatureVector(std::vector<std::string> &FeatureVector, 110 const FeatureBitset &FeatureBits) { 111 for (auto Feature : RISCVFeatureKV) { 112 if (FeatureBits[Feature.Value] && 113 llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key)) 114 FeatureVector.push_back(std::string("+") + Feature.Key); 115 } 116 } 117 118 } // namespace RISCVFeatures 119 120 // Encode VTYPE into the binary format used by the the VSETVLI instruction which 121 // is used by our MC layer representation. 122 // 123 // Bits | Name | Description 124 // -----+------------+------------------------------------------------ 125 // 7 | vma | Vector mask agnostic 126 // 6 | vta | Vector tail agnostic 127 // 5:3 | vsew[2:0] | Standard element width (SEW) setting 128 // 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting 129 unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, 130 bool TailAgnostic, bool MaskAgnostic) { 131 assert(isValidSEW(SEW) && "Invalid SEW"); 132 unsigned VLMULBits = static_cast<unsigned>(VLMUL); 133 unsigned VSEWBits = Log2_32(SEW) - 3; 134 unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7); 135 if (TailAgnostic) 136 VTypeI |= 0x40; 137 if (MaskAgnostic) 138 VTypeI |= 0x80; 139 140 return VTypeI; 141 } 142 143 std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) { 144 switch (VLMUL) { 145 default: 146 llvm_unreachable("Unexpected LMUL value!"); 147 case RISCVII::VLMUL::LMUL_1: 148 case RISCVII::VLMUL::LMUL_2: 149 case RISCVII::VLMUL::LMUL_4: 150 case RISCVII::VLMUL::LMUL_8: 151 return std::make_pair(1 << static_cast<unsigned>(VLMUL), false); 152 case RISCVII::VLMUL::LMUL_F2: 153 case RISCVII::VLMUL::LMUL_F4: 154 case RISCVII::VLMUL::LMUL_F8: 155 return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true); 156 } 157 } 158 159 void RISCVVType::printVType(unsigned VType, raw_ostream &OS) { 160 unsigned Sew = getSEW(VType); 161 OS << "e" << Sew; 162 163 unsigned LMul; 164 bool Fractional; 165 std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType)); 166 167 if (Fractional) 168 OS << ", mf"; 169 else 170 OS << ", m"; 171 OS << LMul; 172 173 if (isTailAgnostic(VType)) 174 OS << ", ta"; 175 else 176 OS << ", tu"; 177 178 if (isMaskAgnostic(VType)) 179 OS << ", ma"; 180 else 181 OS << ", mu"; 182 } 183 184 } // namespace llvm 185