1 //===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone enum definitions for the RISC-V target 10 // useful for the compiler back-end and the MC libraries. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "RISCVBaseInfo.h" 15 #include "llvm/ADT/ArrayRef.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCRegisterInfo.h" 18 #include "llvm/MC/MCSubtargetInfo.h" 19 #include "llvm/Support/raw_ostream.h" 20 #include "llvm/TargetParser/TargetParser.h" 21 #include "llvm/TargetParser/Triple.h" 22 23 namespace llvm { 24 25 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]; 26 27 namespace RISCVSysReg { 28 #define GET_SysRegsList_IMPL 29 #include "RISCVGenSearchableTables.inc" 30 } // namespace RISCVSysReg 31 32 namespace RISCVInsnOpcode { 33 #define GET_RISCVOpcodesList_IMPL 34 #include "RISCVGenSearchableTables.inc" 35 } // namespace RISCVInsnOpcode 36 37 namespace RISCVABI { 38 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, 39 StringRef ABIName) { 40 auto TargetABI = getTargetABI(ABIName); 41 bool IsRV64 = TT.isArch64Bit(); 42 bool IsRVE = FeatureBits[RISCV::FeatureStdExtE]; 43 44 if (!ABIName.empty() && TargetABI == ABI_Unknown) { 45 errs() 46 << "'" << ABIName 47 << "' is not a recognized ABI for this target (ignoring target-abi)\n"; 48 } else if (ABIName.starts_with("ilp32") && IsRV64) { 49 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring " 50 "target-abi)\n"; 51 TargetABI = ABI_Unknown; 52 } else if (ABIName.starts_with("lp64") && !IsRV64) { 53 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring " 54 "target-abi)\n"; 55 TargetABI = ABI_Unknown; 56 } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E && 57 TargetABI != ABI_Unknown) { 58 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser 59 errs() 60 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n"; 61 TargetABI = ABI_Unknown; 62 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E && 63 TargetABI != ABI_Unknown) { 64 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser 65 errs() 66 << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n"; 67 TargetABI = ABI_Unknown; 68 } 69 70 if ((TargetABI == RISCVABI::ABI::ABI_ILP32E || 71 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) && 72 FeatureBits[RISCV::FeatureStdExtD]) 73 report_fatal_error("ILP32E cannot be used with the D ISA extension"); 74 75 if (TargetABI != ABI_Unknown) 76 return TargetABI; 77 78 // If no explicit ABI is given, try to compute the default ABI. 79 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits); 80 if (!ISAInfo) 81 report_fatal_error(ISAInfo.takeError()); 82 return getTargetABI((*ISAInfo)->computeDefaultABI()); 83 } 84 85 ABI getTargetABI(StringRef ABIName) { 86 auto TargetABI = StringSwitch<ABI>(ABIName) 87 .Case("ilp32", ABI_ILP32) 88 .Case("ilp32f", ABI_ILP32F) 89 .Case("ilp32d", ABI_ILP32D) 90 .Case("ilp32e", ABI_ILP32E) 91 .Case("lp64", ABI_LP64) 92 .Case("lp64f", ABI_LP64F) 93 .Case("lp64d", ABI_LP64D) 94 .Case("lp64e", ABI_LP64E) 95 .Default(ABI_Unknown); 96 return TargetABI; 97 } 98 99 // To avoid the BP value clobbered by a function call, we need to choose a 100 // callee saved register to save the value. RV32E only has X8 and X9 as callee 101 // saved registers and X8 will be used as fp. So we choose X9 as bp. 102 MCRegister getBPReg() { return RISCV::X9; } 103 104 // Returns the register holding shadow call stack pointer. 105 MCRegister getSCSPReg() { return RISCV::X3; } 106 107 } // namespace RISCVABI 108 109 namespace RISCVFeatures { 110 111 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { 112 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) 113 report_fatal_error("RV64 target requires an RV64 CPU"); 114 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit]) 115 report_fatal_error("RV32 target requires an RV32 CPU"); 116 if (FeatureBits[RISCV::Feature32Bit] && 117 FeatureBits[RISCV::Feature64Bit]) 118 report_fatal_error("RV32 and RV64 can't be combined"); 119 } 120 121 llvm::Expected<std::unique_ptr<RISCVISAInfo>> 122 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) { 123 unsigned XLen = IsRV64 ? 64 : 32; 124 std::vector<std::string> FeatureVector; 125 // Convert FeatureBitset to FeatureVector. 126 for (auto Feature : RISCVFeatureKV) { 127 if (FeatureBits[Feature.Value] && 128 llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key)) 129 FeatureVector.push_back(std::string("+") + Feature.Key); 130 } 131 return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector); 132 } 133 134 } // namespace RISCVFeatures 135 136 // Include the auto-generated portion of the compress emitter. 137 #define GEN_UNCOMPRESS_INSTR 138 #define GEN_COMPRESS_INSTR 139 #include "RISCVGenCompressInstEmitter.inc" 140 141 bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI, 142 const MCSubtargetInfo &STI) { 143 return compressInst(OutInst, MI, STI); 144 } 145 146 bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI, 147 const MCSubtargetInfo &STI) { 148 return uncompressInst(OutInst, MI, STI); 149 } 150 151 // Lookup table for fli.s for entries 2-31. 152 static constexpr std::pair<uint8_t, uint8_t> LoadFP32ImmArr[] = { 153 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00}, 154 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00}, 155 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10}, 156 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01}, 157 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00}, 158 {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11}, 159 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10}, 160 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00}, 161 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00}, 162 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10}, 163 }; 164 165 int RISCVLoadFPImm::getLoadFPImm(APFloat FPImm) { 166 assert((&FPImm.getSemantics() == &APFloat::IEEEsingle() || 167 &FPImm.getSemantics() == &APFloat::IEEEdouble() || 168 &FPImm.getSemantics() == &APFloat::IEEEhalf()) && 169 "Unexpected semantics"); 170 171 // Handle the minimum normalized value which is different for each type. 172 if (FPImm.isSmallestNormalized() && !FPImm.isNegative()) 173 return 1; 174 175 // Convert to single precision to use its lookup table. 176 bool LosesInfo; 177 APFloat::opStatus Status = FPImm.convert( 178 APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &LosesInfo); 179 if (Status != APFloat::opOK || LosesInfo) 180 return -1; 181 182 APInt Imm = FPImm.bitcastToAPInt(); 183 184 if (Imm.extractBitsAsZExtValue(21, 0) != 0) 185 return -1; 186 187 bool Sign = Imm.extractBitsAsZExtValue(1, 31); 188 uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21); 189 uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23); 190 191 auto EMI = llvm::lower_bound(LoadFP32ImmArr, std::make_pair(Exp, Mantissa)); 192 if (EMI == std::end(LoadFP32ImmArr) || EMI->first != Exp || 193 EMI->second != Mantissa) 194 return -1; 195 196 // Table doesn't have entry 0 or 1. 197 int Entry = std::distance(std::begin(LoadFP32ImmArr), EMI) + 2; 198 199 // The only legal negative value is -1.0(entry 0). 1.0 is entry 16. 200 if (Sign) { 201 if (Entry == 16) 202 return 0; 203 return -1; 204 } 205 206 return Entry; 207 } 208 209 float RISCVLoadFPImm::getFPImm(unsigned Imm) { 210 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate"); 211 212 // Entry 0 is -1.0, the only negative value. Entry 16 is 1.0. 213 uint32_t Sign = 0; 214 if (Imm == 0) { 215 Sign = 0b1; 216 Imm = 16; 217 } 218 219 uint32_t Exp = LoadFP32ImmArr[Imm - 2].first; 220 uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second; 221 222 uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21; 223 return bit_cast<float>(I); 224 } 225 226 void RISCVZC::printRlist(unsigned SlistEncode, raw_ostream &OS) { 227 OS << "{ra"; 228 if (SlistEncode > 4) { 229 OS << ", s0"; 230 if (SlistEncode == 15) 231 OS << "-s11"; 232 else if (SlistEncode > 5 && SlistEncode <= 14) 233 OS << "-s" << (SlistEncode - 5); 234 } 235 OS << "}"; 236 } 237 238 } // namespace llvm 239