1 //===-- RISCVBaseInfo.cpp - Top level definitions for RISCV MC ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone enum definitions for the RISCV target 10 // useful for the compiler back-end and the MC libraries. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "RISCVBaseInfo.h" 15 #include "llvm/ADT/ArrayRef.h" 16 #include "llvm/ADT/Triple.h" 17 #include "llvm/Support/raw_ostream.h" 18 19 namespace llvm { 20 namespace RISCVSysReg { 21 #define GET_SysRegsList_IMPL 22 #include "RISCVGenSearchableTables.inc" 23 } // namespace RISCVSysReg 24 25 namespace RISCVABI { 26 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, 27 StringRef ABIName) { 28 auto TargetABI = getTargetABI(ABIName); 29 bool IsRV64 = TT.isArch64Bit(); 30 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; 31 32 if (!ABIName.empty() && TargetABI == ABI_Unknown) { 33 errs() 34 << "'" << ABIName 35 << "' is not a recognized ABI for this target (ignoring target-abi)\n"; 36 } else if (ABIName.startswith("ilp32") && IsRV64) { 37 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring " 38 "target-abi)\n"; 39 TargetABI = ABI_Unknown; 40 } else if (ABIName.startswith("lp64") && !IsRV64) { 41 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring " 42 "target-abi)\n"; 43 TargetABI = ABI_Unknown; 44 } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) { 45 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser 46 errs() 47 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n"; 48 TargetABI = ABI_Unknown; 49 } 50 51 if (TargetABI != ABI_Unknown) 52 return TargetABI; 53 54 // For now, default to the ilp32/ilp32e/lp64 ABI if no explicit ABI is given 55 // or an invalid/unrecognised string is given. In the future, it might be 56 // worth changing this to default to ilp32f/lp64f and ilp32d/lp64d when 57 // hardware support for floating point is present. 58 if (IsRV32E) 59 return ABI_ILP32E; 60 if (IsRV64) 61 return ABI_LP64; 62 return ABI_ILP32; 63 } 64 65 ABI getTargetABI(StringRef ABIName) { 66 auto TargetABI = StringSwitch<ABI>(ABIName) 67 .Case("ilp32", ABI_ILP32) 68 .Case("ilp32f", ABI_ILP32F) 69 .Case("ilp32d", ABI_ILP32D) 70 .Case("ilp32e", ABI_ILP32E) 71 .Case("lp64", ABI_LP64) 72 .Case("lp64f", ABI_LP64F) 73 .Case("lp64d", ABI_LP64D) 74 .Default(ABI_Unknown); 75 return TargetABI; 76 } 77 78 // To avoid the BP value clobbered by a function call, we need to choose a 79 // callee saved register to save the value. RV32E only has X8 and X9 as callee 80 // saved registers and X8 will be used as fp. So we choose X9 as bp. 81 MCRegister getBPReg() { return RISCV::X9; } 82 83 // Returns the register holding shadow call stack pointer. 84 MCRegister getSCSPReg() { return RISCV::X18; } 85 86 } // namespace RISCVABI 87 88 namespace RISCVFeatures { 89 90 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { 91 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) 92 report_fatal_error("RV32E can't be enabled for an RV64 target"); 93 } 94 95 } // namespace RISCVFeatures 96 97 namespace RISCVVPseudosTable { 98 99 #define GET_RISCVVPseudosTable_IMPL 100 #include "RISCVGenSearchableTables.inc" 101 102 } // namespace RISCVVPseudosTable 103 104 void RISCVVType::printVType(unsigned VType, raw_ostream &OS) { 105 RISCVVSEW VSEW = getVSEW(VType); 106 RISCVVLMUL VLMUL = getVLMUL(VType); 107 108 unsigned Sew = 1 << (static_cast<unsigned>(VSEW) + 3); 109 OS << "e" << Sew; 110 111 switch (VLMUL) { 112 case RISCVVLMUL::LMUL_RESERVED: 113 llvm_unreachable("Unexpected LMUL value!"); 114 case RISCVVLMUL::LMUL_1: 115 case RISCVVLMUL::LMUL_2: 116 case RISCVVLMUL::LMUL_4: 117 case RISCVVLMUL::LMUL_8: { 118 unsigned LMul = 1 << static_cast<unsigned>(VLMUL); 119 OS << ",m" << LMul; 120 break; 121 } 122 case RISCVVLMUL::LMUL_F2: 123 case RISCVVLMUL::LMUL_F4: 124 case RISCVVLMUL::LMUL_F8: { 125 unsigned LMul = 1 << (8 - static_cast<unsigned>(VLMUL)); 126 OS << ",mf" << LMul; 127 break; 128 } 129 } 130 131 if (isTailAgnostic(VType)) 132 OS << ",ta"; 133 else 134 OS << ",tu"; 135 136 if (isMaskAgnostic(VType)) 137 OS << ",ma"; 138 else 139 OS << ",mu"; 140 } 141 142 } // namespace llvm 143