1 //===-- RISCVAsmBackend.h - RISC-V Assembler Backend ----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H 10 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H 11 12 #include "MCTargetDesc/RISCVBaseInfo.h" 13 #include "MCTargetDesc/RISCVFixupKinds.h" 14 #include "MCTargetDesc/RISCVMCTargetDesc.h" 15 #include "llvm/MC/MCAsmBackend.h" 16 #include "llvm/MC/MCFixupKindInfo.h" 17 #include "llvm/MC/MCSubtargetInfo.h" 18 19 namespace llvm { 20 class MCAssembler; 21 class MCObjectTargetWriter; 22 class raw_ostream; 23 24 class RISCVAsmBackend : public MCAsmBackend { 25 const MCSubtargetInfo &STI; 26 uint8_t OSABI; 27 bool Is64Bit; 28 bool ForceRelocs = false; 29 const MCTargetOptions &TargetOptions; 30 31 public: 32 RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, 33 const MCTargetOptions &Options) 34 : MCAsmBackend(support::little, RISCV::fixup_riscv_relax), STI(STI), 35 OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) { 36 RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits()); 37 } 38 ~RISCVAsmBackend() override = default; 39 40 void setForceRelocs() { ForceRelocs = true; } 41 42 // Return Size with extra Nop Bytes for alignment directive in code section. 43 bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF, 44 unsigned &Size) override; 45 46 // Insert target specific fixup type for alignment directive in code section. 47 bool shouldInsertFixupForCodeAlign(MCAssembler &Asm, 48 const MCAsmLayout &Layout, 49 MCAlignFragment &AF) override; 50 51 bool evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout, 52 const MCFixup &Fixup, const MCFragment *DF, 53 const MCValue &Target, uint64_t &Value, 54 bool &WasForced) override; 55 56 bool handleAddSubRelocations(const MCAsmLayout &Layout, const MCFragment &F, 57 const MCFixup &Fixup, const MCValue &Target, 58 uint64_t &FixedValue) const override; 59 60 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 61 const MCValue &Target, MutableArrayRef<char> Data, 62 uint64_t Value, bool IsResolved, 63 const MCSubtargetInfo *STI) const override; 64 65 std::unique_ptr<MCObjectTargetWriter> 66 createObjectTargetWriter() const override; 67 68 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 69 const MCValue &Target) override; 70 71 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 72 const MCRelaxableFragment *DF, 73 const MCAsmLayout &Layout) const override { 74 llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced"); 75 } 76 77 bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, 78 uint64_t Value, 79 const MCRelaxableFragment *DF, 80 const MCAsmLayout &Layout, 81 const bool WasForced) const override; 82 83 unsigned getNumFixupKinds() const override { 84 return RISCV::NumTargetFixupKinds; 85 } 86 87 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override; 88 89 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; 90 91 bool mayNeedRelaxation(const MCInst &Inst, 92 const MCSubtargetInfo &STI) const override; 93 unsigned getRelaxedOpcode(unsigned Op) const; 94 95 void relaxInstruction(MCInst &Inst, 96 const MCSubtargetInfo &STI) const override; 97 98 bool relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, MCAsmLayout &Layout, 99 bool &WasRelaxed) const override; 100 bool relaxDwarfCFA(MCDwarfCallFrameFragment &DF, MCAsmLayout &Layout, 101 bool &WasRelaxed) const override; 102 103 bool writeNopData(raw_ostream &OS, uint64_t Count, 104 const MCSubtargetInfo *STI) const override; 105 106 const MCTargetOptions &getTargetOptions() const { return TargetOptions; } 107 }; 108 } 109 110 #endif 111