1 //===-- RISCVAsmBackend.h - RISCV Assembler Backend -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H 10 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H 11 12 #include "MCTargetDesc/RISCVBaseInfo.h" 13 #include "MCTargetDesc/RISCVFixupKinds.h" 14 #include "MCTargetDesc/RISCVMCTargetDesc.h" 15 #include "llvm/MC/MCAsmBackend.h" 16 #include "llvm/MC/MCFixupKindInfo.h" 17 #include "llvm/MC/MCSubtargetInfo.h" 18 19 namespace llvm { 20 class MCAssembler; 21 class MCObjectTargetWriter; 22 class raw_ostream; 23 24 class RISCVAsmBackend : public MCAsmBackend { 25 const MCSubtargetInfo &STI; 26 uint8_t OSABI; 27 bool Is64Bit; 28 bool ForceRelocs = false; 29 const MCTargetOptions &TargetOptions; 30 RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown; 31 32 public: 33 RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, 34 const MCTargetOptions &Options) 35 : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), 36 TargetOptions(Options) { 37 TargetABI = RISCVABI::computeTargetABI( 38 STI.getTargetTriple(), STI.getFeatureBits(), Options.getABIName()); 39 RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits()); 40 } 41 ~RISCVAsmBackend() override {} 42 43 void setForceRelocs() { ForceRelocs = true; } 44 45 // Return Size with extra Nop Bytes for alignment directive in code section. 46 bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF, 47 unsigned &Size) override; 48 49 // Insert target specific fixup type for alignment directive in code section. 50 bool shouldInsertFixupForCodeAlign(MCAssembler &Asm, 51 const MCAsmLayout &Layout, 52 MCAlignFragment &AF) override; 53 54 bool evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout, 55 const MCFixup &Fixup, const MCFragment *DF, 56 const MCValue &Target, uint64_t &Value, 57 bool &WasForced) override; 58 59 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 60 const MCValue &Target, MutableArrayRef<char> Data, 61 uint64_t Value, bool IsResolved, 62 const MCSubtargetInfo *STI) const override; 63 64 std::unique_ptr<MCObjectTargetWriter> 65 createObjectTargetWriter() const override; 66 67 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 68 const MCValue &Target) override; 69 70 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 71 const MCRelaxableFragment *DF, 72 const MCAsmLayout &Layout) const override { 73 llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced"); 74 } 75 76 bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, 77 uint64_t Value, 78 const MCRelaxableFragment *DF, 79 const MCAsmLayout &Layout, 80 const bool WasForced) const override; 81 82 unsigned getNumFixupKinds() const override { 83 return RISCV::NumTargetFixupKinds; 84 } 85 86 Optional<MCFixupKind> getFixupKind(StringRef Name) const override; 87 88 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; 89 90 bool mayNeedRelaxation(const MCInst &Inst, 91 const MCSubtargetInfo &STI) const override; 92 unsigned getRelaxedOpcode(unsigned Op) const; 93 94 void relaxInstruction(MCInst &Inst, 95 const MCSubtargetInfo &STI) const override; 96 97 bool relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, MCAsmLayout &Layout, 98 bool &WasRelaxed) const override; 99 bool relaxDwarfCFA(MCDwarfCallFrameFragment &DF, MCAsmLayout &Layout, 100 bool &WasRelaxed) const override; 101 102 bool writeNopData(raw_ostream &OS, uint64_t Count, 103 const MCSubtargetInfo *STI) const override; 104 105 const MCTargetOptions &getTargetOptions() const { return TargetOptions; } 106 RISCVABI::ABI getTargetABI() const { return TargetABI; } 107 }; 108 } 109 110 #endif 111