1 //===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "RISCVAsmBackend.h" 10 #include "RISCVMCExpr.h" 11 #include "llvm/ADT/APInt.h" 12 #include "llvm/MC/MCAssembler.h" 13 #include "llvm/MC/MCContext.h" 14 #include "llvm/MC/MCDirectives.h" 15 #include "llvm/MC/MCELFObjectWriter.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/MC/MCObjectWriter.h" 18 #include "llvm/MC/MCSymbol.h" 19 #include "llvm/MC/MCValue.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/Support/raw_ostream.h" 22 23 using namespace llvm; 24 25 // If linker relaxation is enabled, or the relax option had previously been 26 // enabled, always emit relocations even if the fixup can be resolved. This is 27 // necessary for correctness as offsets may change during relaxation. 28 bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm, 29 const MCFixup &Fixup, 30 const MCValue &Target) { 31 bool ShouldForce = false; 32 33 switch ((unsigned)Fixup.getKind()) { 34 default: 35 break; 36 case FK_Data_1: 37 case FK_Data_2: 38 case FK_Data_4: 39 case FK_Data_8: 40 if (Target.isAbsolute()) 41 return false; 42 break; 43 case RISCV::fixup_riscv_got_hi20: 44 case RISCV::fixup_riscv_tls_got_hi20: 45 case RISCV::fixup_riscv_tls_gd_hi20: 46 return true; 47 case RISCV::fixup_riscv_pcrel_lo12_i: 48 case RISCV::fixup_riscv_pcrel_lo12_s: 49 // For pcrel_lo12, force a relocation if the target of the corresponding 50 // pcrel_hi20 is not in the same fragment. 51 const MCFixup *T = cast<RISCVMCExpr>(Fixup.getValue())->getPCRelHiFixup(); 52 if (!T) { 53 Asm.getContext().reportError(Fixup.getLoc(), 54 "could not find corresponding %pcrel_hi"); 55 return false; 56 } 57 58 switch ((unsigned)T->getKind()) { 59 default: 60 llvm_unreachable("Unexpected fixup kind for pcrel_lo12"); 61 break; 62 case RISCV::fixup_riscv_got_hi20: 63 case RISCV::fixup_riscv_tls_got_hi20: 64 case RISCV::fixup_riscv_tls_gd_hi20: 65 ShouldForce = true; 66 break; 67 case RISCV::fixup_riscv_pcrel_hi20: { 68 MCFragment *TFragment = T->getValue()->findAssociatedFragment(); 69 MCFragment *FixupFragment = Fixup.getValue()->findAssociatedFragment(); 70 assert(FixupFragment && "We should have a fragment for this fixup"); 71 ShouldForce = 72 !TFragment || TFragment->getParent() != FixupFragment->getParent(); 73 break; 74 } 75 } 76 break; 77 } 78 79 return ShouldForce || STI.getFeatureBits()[RISCV::FeatureRelax] || 80 ForceRelocs; 81 } 82 83 bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, 84 bool Resolved, 85 uint64_t Value, 86 const MCRelaxableFragment *DF, 87 const MCAsmLayout &Layout, 88 const bool WasForced) const { 89 // Return true if the symbol is actually unresolved. 90 // Resolved could be always false when shouldForceRelocation return true. 91 // We use !WasForced to indicate that the symbol is unresolved and not forced 92 // by shouldForceRelocation. 93 if (!Resolved && !WasForced) 94 return true; 95 96 int64_t Offset = int64_t(Value); 97 switch ((unsigned)Fixup.getKind()) { 98 default: 99 return false; 100 case RISCV::fixup_riscv_rvc_branch: 101 // For compressed branch instructions the immediate must be 102 // in the range [-256, 254]. 103 return Offset > 254 || Offset < -256; 104 case RISCV::fixup_riscv_rvc_jump: 105 // For compressed jump instructions the immediate must be 106 // in the range [-2048, 2046]. 107 return Offset > 2046 || Offset < -2048; 108 } 109 } 110 111 void RISCVAsmBackend::relaxInstruction(const MCInst &Inst, 112 const MCSubtargetInfo &STI, 113 MCInst &Res) const { 114 // TODO: replace this with call to auto generated uncompressinstr() function. 115 switch (Inst.getOpcode()) { 116 default: 117 llvm_unreachable("Opcode not expected!"); 118 case RISCV::C_BEQZ: 119 // c.beqz $rs1, $imm -> beq $rs1, X0, $imm. 120 Res.setOpcode(RISCV::BEQ); 121 Res.addOperand(Inst.getOperand(0)); 122 Res.addOperand(MCOperand::createReg(RISCV::X0)); 123 Res.addOperand(Inst.getOperand(1)); 124 break; 125 case RISCV::C_BNEZ: 126 // c.bnez $rs1, $imm -> bne $rs1, X0, $imm. 127 Res.setOpcode(RISCV::BNE); 128 Res.addOperand(Inst.getOperand(0)); 129 Res.addOperand(MCOperand::createReg(RISCV::X0)); 130 Res.addOperand(Inst.getOperand(1)); 131 break; 132 case RISCV::C_J: 133 // c.j $imm -> jal X0, $imm. 134 Res.setOpcode(RISCV::JAL); 135 Res.addOperand(MCOperand::createReg(RISCV::X0)); 136 Res.addOperand(Inst.getOperand(0)); 137 break; 138 case RISCV::C_JAL: 139 // c.jal $imm -> jal X1, $imm. 140 Res.setOpcode(RISCV::JAL); 141 Res.addOperand(MCOperand::createReg(RISCV::X1)); 142 Res.addOperand(Inst.getOperand(0)); 143 break; 144 } 145 } 146 147 // Given a compressed control flow instruction this function returns 148 // the expanded instruction. 149 unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const { 150 switch (Op) { 151 default: 152 return Op; 153 case RISCV::C_BEQZ: 154 return RISCV::BEQ; 155 case RISCV::C_BNEZ: 156 return RISCV::BNE; 157 case RISCV::C_J: 158 case RISCV::C_JAL: // fall through. 159 return RISCV::JAL; 160 } 161 } 162 163 bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst, 164 const MCSubtargetInfo &STI) const { 165 return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode(); 166 } 167 168 bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const { 169 bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC]; 170 unsigned MinNopLen = HasStdExtC ? 2 : 4; 171 172 if ((Count % MinNopLen) != 0) 173 return false; 174 175 // The canonical nop on RISC-V is addi x0, x0, 0. 176 for (; Count >= 4; Count -= 4) 177 OS.write("\x13\0\0\0", 4); 178 179 // The canonical nop on RVC is c.nop. 180 if (Count && HasStdExtC) 181 OS.write("\x01\0", 2); 182 183 return true; 184 } 185 186 static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 187 MCContext &Ctx) { 188 unsigned Kind = Fixup.getKind(); 189 switch (Kind) { 190 default: 191 llvm_unreachable("Unknown fixup kind!"); 192 case RISCV::fixup_riscv_got_hi20: 193 case RISCV::fixup_riscv_tls_got_hi20: 194 case RISCV::fixup_riscv_tls_gd_hi20: 195 llvm_unreachable("Relocation should be unconditionally forced\n"); 196 case FK_Data_1: 197 case FK_Data_2: 198 case FK_Data_4: 199 case FK_Data_8: 200 case FK_Data_6b: 201 return Value; 202 case RISCV::fixup_riscv_lo12_i: 203 case RISCV::fixup_riscv_pcrel_lo12_i: 204 case RISCV::fixup_riscv_tprel_lo12_i: 205 return Value & 0xfff; 206 case RISCV::fixup_riscv_lo12_s: 207 case RISCV::fixup_riscv_pcrel_lo12_s: 208 case RISCV::fixup_riscv_tprel_lo12_s: 209 return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7); 210 case RISCV::fixup_riscv_hi20: 211 case RISCV::fixup_riscv_pcrel_hi20: 212 case RISCV::fixup_riscv_tprel_hi20: 213 // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative. 214 return ((Value + 0x800) >> 12) & 0xfffff; 215 case RISCV::fixup_riscv_jal: { 216 if (!isInt<21>(Value)) 217 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 218 if (Value & 0x1) 219 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned"); 220 // Need to produce imm[19|10:1|11|19:12] from the 21-bit Value. 221 unsigned Sbit = (Value >> 20) & 0x1; 222 unsigned Hi8 = (Value >> 12) & 0xff; 223 unsigned Mid1 = (Value >> 11) & 0x1; 224 unsigned Lo10 = (Value >> 1) & 0x3ff; 225 // Inst{31} = Sbit; 226 // Inst{30-21} = Lo10; 227 // Inst{20} = Mid1; 228 // Inst{19-12} = Hi8; 229 Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8; 230 return Value; 231 } 232 case RISCV::fixup_riscv_branch: { 233 if (!isInt<13>(Value)) 234 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 235 if (Value & 0x1) 236 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned"); 237 // Need to extract imm[12], imm[10:5], imm[4:1], imm[11] from the 13-bit 238 // Value. 239 unsigned Sbit = (Value >> 12) & 0x1; 240 unsigned Hi1 = (Value >> 11) & 0x1; 241 unsigned Mid6 = (Value >> 5) & 0x3f; 242 unsigned Lo4 = (Value >> 1) & 0xf; 243 // Inst{31} = Sbit; 244 // Inst{30-25} = Mid6; 245 // Inst{11-8} = Lo4; 246 // Inst{7} = Hi1; 247 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7); 248 return Value; 249 } 250 case RISCV::fixup_riscv_call: 251 case RISCV::fixup_riscv_call_plt: { 252 // Jalr will add UpperImm with the sign-extended 12-bit LowerImm, 253 // we need to add 0x800ULL before extract upper bits to reflect the 254 // effect of the sign extension. 255 uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL; 256 uint64_t LowerImm = Value & 0xfffULL; 257 return UpperImm | ((LowerImm << 20) << 32); 258 } 259 case RISCV::fixup_riscv_rvc_jump: { 260 // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value. 261 unsigned Bit11 = (Value >> 11) & 0x1; 262 unsigned Bit4 = (Value >> 4) & 0x1; 263 unsigned Bit9_8 = (Value >> 8) & 0x3; 264 unsigned Bit10 = (Value >> 10) & 0x1; 265 unsigned Bit6 = (Value >> 6) & 0x1; 266 unsigned Bit7 = (Value >> 7) & 0x1; 267 unsigned Bit3_1 = (Value >> 1) & 0x7; 268 unsigned Bit5 = (Value >> 5) & 0x1; 269 Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) | 270 (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5; 271 return Value; 272 } 273 case RISCV::fixup_riscv_rvc_branch: { 274 // Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5] 275 unsigned Bit8 = (Value >> 8) & 0x1; 276 unsigned Bit7_6 = (Value >> 6) & 0x3; 277 unsigned Bit5 = (Value >> 5) & 0x1; 278 unsigned Bit4_3 = (Value >> 3) & 0x3; 279 unsigned Bit2_1 = (Value >> 1) & 0x3; 280 Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) | 281 (Bit5 << 2); 282 return Value; 283 } 284 285 } 286 } 287 288 void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 289 const MCValue &Target, 290 MutableArrayRef<char> Data, uint64_t Value, 291 bool IsResolved, 292 const MCSubtargetInfo *STI) const { 293 MCContext &Ctx = Asm.getContext(); 294 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind()); 295 if (!Value) 296 return; // Doesn't change encoding. 297 // Apply any target-specific value adjustments. 298 Value = adjustFixupValue(Fixup, Value, Ctx); 299 300 // Shift the value into position. 301 Value <<= Info.TargetOffset; 302 303 unsigned Offset = Fixup.getOffset(); 304 unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8; 305 306 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!"); 307 308 // For each byte of the fragment that the fixup touches, mask in the 309 // bits from the fixup value. 310 for (unsigned i = 0; i != NumBytes; ++i) { 311 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 312 } 313 } 314 315 // Linker relaxation may change code size. We have to insert Nops 316 // for .align directive when linker relaxation enabled. So then Linker 317 // could satisfy alignment by removing Nops. 318 // The function return the total Nops Size we need to insert. 319 bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign( 320 const MCAlignFragment &AF, unsigned &Size) { 321 // Calculate Nops Size only when linker relaxation enabled. 322 if (!STI.getFeatureBits()[RISCV::FeatureRelax]) 323 return false; 324 325 bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC]; 326 unsigned MinNopLen = HasStdExtC ? 2 : 4; 327 328 if (AF.getAlignment() <= MinNopLen) { 329 return false; 330 } else { 331 Size = AF.getAlignment() - MinNopLen; 332 return true; 333 } 334 } 335 336 // We need to insert R_RISCV_ALIGN relocation type to indicate the 337 // position of Nops and the total bytes of the Nops have been inserted 338 // when linker relaxation enabled. 339 // The function insert fixup_riscv_align fixup which eventually will 340 // transfer to R_RISCV_ALIGN relocation type. 341 bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm, 342 const MCAsmLayout &Layout, 343 MCAlignFragment &AF) { 344 // Insert the fixup only when linker relaxation enabled. 345 if (!STI.getFeatureBits()[RISCV::FeatureRelax]) 346 return false; 347 348 // Calculate total Nops we need to insert. If there are none to insert 349 // then simply return. 350 unsigned Count; 351 if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count) || (Count == 0)) 352 return false; 353 354 MCContext &Ctx = Asm.getContext(); 355 const MCExpr *Dummy = MCConstantExpr::create(0, Ctx); 356 // Create fixup_riscv_align fixup. 357 MCFixup Fixup = 358 MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_align), SMLoc()); 359 360 uint64_t FixedValue = 0; 361 MCValue NopBytes = MCValue::get(Count); 362 363 Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, NopBytes, 364 FixedValue); 365 366 return true; 367 } 368 369 std::unique_ptr<MCObjectTargetWriter> 370 RISCVAsmBackend::createObjectTargetWriter() const { 371 return createRISCVELFObjectWriter(OSABI, Is64Bit); 372 } 373 374 MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T, 375 const MCSubtargetInfo &STI, 376 const MCRegisterInfo &MRI, 377 const MCTargetOptions &Options) { 378 const Triple &TT = STI.getTargetTriple(); 379 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); 380 return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options); 381 } 382