1//=-- RISCVRegisterBank.td - Describe the RISC-V Banks -------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12/// General Purpose Registers: X. 13def GPRBRegBank : RegisterBank<"GPRB", [GPR]>; 14 15/// Floating Point Registers: F. 16def FPRBRegBank : RegisterBank<"FPRB", [FPR64]>; 17 18/// Vector Registers : V. 19def VRBRegBank : RegisterBank<"VRB", [VRM8]>; 20 21