1 //===-- PPCTargetTransformInfo.cpp - PPC specific TTI ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "PPCTargetTransformInfo.h" 10 #include "llvm/Analysis/CodeMetrics.h" 11 #include "llvm/Analysis/TargetLibraryInfo.h" 12 #include "llvm/Analysis/TargetTransformInfo.h" 13 #include "llvm/CodeGen/BasicTTIImpl.h" 14 #include "llvm/CodeGen/CostTable.h" 15 #include "llvm/CodeGen/TargetLowering.h" 16 #include "llvm/CodeGen/TargetSchedule.h" 17 #include "llvm/IR/IntrinsicsPowerPC.h" 18 #include "llvm/Support/CommandLine.h" 19 #include "llvm/Support/Debug.h" 20 #include "llvm/Support/KnownBits.h" 21 #include "llvm/Transforms/InstCombine/InstCombiner.h" 22 #include "llvm/Transforms/Utils/Local.h" 23 24 using namespace llvm; 25 26 #define DEBUG_TYPE "ppctti" 27 28 static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting", 29 cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden); 30 31 // This is currently only used for the data prefetch pass 32 static cl::opt<unsigned> 33 CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64), 34 cl::desc("The loop prefetch cache line size")); 35 36 static cl::opt<bool> 37 EnablePPCColdCC("ppc-enable-coldcc", cl::Hidden, cl::init(false), 38 cl::desc("Enable using coldcc calling conv for cold " 39 "internal functions")); 40 41 static cl::opt<bool> 42 LsrNoInsnsCost("ppc-lsr-no-insns-cost", cl::Hidden, cl::init(false), 43 cl::desc("Do not add instruction count to lsr cost model")); 44 45 // The latency of mtctr is only justified if there are more than 4 46 // comparisons that will be removed as a result. 47 static cl::opt<unsigned> 48 SmallCTRLoopThreshold("min-ctr-loop-threshold", cl::init(4), cl::Hidden, 49 cl::desc("Loops with a constant trip count smaller than " 50 "this value will not use the count register.")); 51 52 //===----------------------------------------------------------------------===// 53 // 54 // PPC cost model. 55 // 56 //===----------------------------------------------------------------------===// 57 58 TargetTransformInfo::PopcntSupportKind 59 PPCTTIImpl::getPopcntSupport(unsigned TyWidth) { 60 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 61 if (ST->hasPOPCNTD() != PPCSubtarget::POPCNTD_Unavailable && TyWidth <= 64) 62 return ST->hasPOPCNTD() == PPCSubtarget::POPCNTD_Slow ? 63 TTI::PSK_SlowHardware : TTI::PSK_FastHardware; 64 return TTI::PSK_Software; 65 } 66 67 Optional<Instruction *> 68 PPCTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { 69 Intrinsic::ID IID = II.getIntrinsicID(); 70 switch (IID) { 71 default: 72 break; 73 case Intrinsic::ppc_altivec_lvx: 74 case Intrinsic::ppc_altivec_lvxl: 75 // Turn PPC lvx -> load if the pointer is known aligned. 76 if (getOrEnforceKnownAlignment( 77 II.getArgOperand(0), Align(16), IC.getDataLayout(), &II, 78 &IC.getAssumptionCache(), &IC.getDominatorTree()) >= 16) { 79 Value *Ptr = IC.Builder.CreateBitCast( 80 II.getArgOperand(0), PointerType::getUnqual(II.getType())); 81 return new LoadInst(II.getType(), Ptr, "", false, Align(16)); 82 } 83 break; 84 case Intrinsic::ppc_vsx_lxvw4x: 85 case Intrinsic::ppc_vsx_lxvd2x: { 86 // Turn PPC VSX loads into normal loads. 87 Value *Ptr = IC.Builder.CreateBitCast(II.getArgOperand(0), 88 PointerType::getUnqual(II.getType())); 89 return new LoadInst(II.getType(), Ptr, Twine(""), false, Align(1)); 90 } 91 case Intrinsic::ppc_altivec_stvx: 92 case Intrinsic::ppc_altivec_stvxl: 93 // Turn stvx -> store if the pointer is known aligned. 94 if (getOrEnforceKnownAlignment( 95 II.getArgOperand(1), Align(16), IC.getDataLayout(), &II, 96 &IC.getAssumptionCache(), &IC.getDominatorTree()) >= 16) { 97 Type *OpPtrTy = PointerType::getUnqual(II.getArgOperand(0)->getType()); 98 Value *Ptr = IC.Builder.CreateBitCast(II.getArgOperand(1), OpPtrTy); 99 return new StoreInst(II.getArgOperand(0), Ptr, false, Align(16)); 100 } 101 break; 102 case Intrinsic::ppc_vsx_stxvw4x: 103 case Intrinsic::ppc_vsx_stxvd2x: { 104 // Turn PPC VSX stores into normal stores. 105 Type *OpPtrTy = PointerType::getUnqual(II.getArgOperand(0)->getType()); 106 Value *Ptr = IC.Builder.CreateBitCast(II.getArgOperand(1), OpPtrTy); 107 return new StoreInst(II.getArgOperand(0), Ptr, false, Align(1)); 108 } 109 case Intrinsic::ppc_altivec_vperm: 110 // Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant. 111 // Note that ppc_altivec_vperm has a big-endian bias, so when creating 112 // a vectorshuffle for little endian, we must undo the transformation 113 // performed on vec_perm in altivec.h. That is, we must complement 114 // the permutation mask with respect to 31 and reverse the order of 115 // V1 and V2. 116 if (Constant *Mask = dyn_cast<Constant>(II.getArgOperand(2))) { 117 assert(cast<FixedVectorType>(Mask->getType())->getNumElements() == 16 && 118 "Bad type for intrinsic!"); 119 120 // Check that all of the elements are integer constants or undefs. 121 bool AllEltsOk = true; 122 for (unsigned i = 0; i != 16; ++i) { 123 Constant *Elt = Mask->getAggregateElement(i); 124 if (!Elt || !(isa<ConstantInt>(Elt) || isa<UndefValue>(Elt))) { 125 AllEltsOk = false; 126 break; 127 } 128 } 129 130 if (AllEltsOk) { 131 // Cast the input vectors to byte vectors. 132 Value *Op0 = 133 IC.Builder.CreateBitCast(II.getArgOperand(0), Mask->getType()); 134 Value *Op1 = 135 IC.Builder.CreateBitCast(II.getArgOperand(1), Mask->getType()); 136 Value *Result = UndefValue::get(Op0->getType()); 137 138 // Only extract each element once. 139 Value *ExtractedElts[32]; 140 memset(ExtractedElts, 0, sizeof(ExtractedElts)); 141 142 for (unsigned i = 0; i != 16; ++i) { 143 if (isa<UndefValue>(Mask->getAggregateElement(i))) 144 continue; 145 unsigned Idx = 146 cast<ConstantInt>(Mask->getAggregateElement(i))->getZExtValue(); 147 Idx &= 31; // Match the hardware behavior. 148 if (DL.isLittleEndian()) 149 Idx = 31 - Idx; 150 151 if (!ExtractedElts[Idx]) { 152 Value *Op0ToUse = (DL.isLittleEndian()) ? Op1 : Op0; 153 Value *Op1ToUse = (DL.isLittleEndian()) ? Op0 : Op1; 154 ExtractedElts[Idx] = IC.Builder.CreateExtractElement( 155 Idx < 16 ? Op0ToUse : Op1ToUse, IC.Builder.getInt32(Idx & 15)); 156 } 157 158 // Insert this value into the result vector. 159 Result = IC.Builder.CreateInsertElement(Result, ExtractedElts[Idx], 160 IC.Builder.getInt32(i)); 161 } 162 return CastInst::Create(Instruction::BitCast, Result, II.getType()); 163 } 164 } 165 break; 166 } 167 return None; 168 } 169 170 InstructionCost PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 171 TTI::TargetCostKind CostKind) { 172 if (DisablePPCConstHoist) 173 return BaseT::getIntImmCost(Imm, Ty, CostKind); 174 175 assert(Ty->isIntegerTy()); 176 177 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 178 if (BitSize == 0) 179 return ~0U; 180 181 if (Imm == 0) 182 return TTI::TCC_Free; 183 184 if (Imm.getBitWidth() <= 64) { 185 if (isInt<16>(Imm.getSExtValue())) 186 return TTI::TCC_Basic; 187 188 if (isInt<32>(Imm.getSExtValue())) { 189 // A constant that can be materialized using lis. 190 if ((Imm.getZExtValue() & 0xFFFF) == 0) 191 return TTI::TCC_Basic; 192 193 return 2 * TTI::TCC_Basic; 194 } 195 } 196 197 return 4 * TTI::TCC_Basic; 198 } 199 200 InstructionCost PPCTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 201 const APInt &Imm, Type *Ty, 202 TTI::TargetCostKind CostKind) { 203 if (DisablePPCConstHoist) 204 return BaseT::getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind); 205 206 assert(Ty->isIntegerTy()); 207 208 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 209 if (BitSize == 0) 210 return ~0U; 211 212 switch (IID) { 213 default: 214 return TTI::TCC_Free; 215 case Intrinsic::sadd_with_overflow: 216 case Intrinsic::uadd_with_overflow: 217 case Intrinsic::ssub_with_overflow: 218 case Intrinsic::usub_with_overflow: 219 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue())) 220 return TTI::TCC_Free; 221 break; 222 case Intrinsic::experimental_stackmap: 223 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 224 return TTI::TCC_Free; 225 break; 226 case Intrinsic::experimental_patchpoint_void: 227 case Intrinsic::experimental_patchpoint_i64: 228 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 229 return TTI::TCC_Free; 230 break; 231 } 232 return PPCTTIImpl::getIntImmCost(Imm, Ty, CostKind); 233 } 234 235 InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 236 const APInt &Imm, Type *Ty, 237 TTI::TargetCostKind CostKind, 238 Instruction *Inst) { 239 if (DisablePPCConstHoist) 240 return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst); 241 242 assert(Ty->isIntegerTy()); 243 244 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 245 if (BitSize == 0) 246 return ~0U; 247 248 unsigned ImmIdx = ~0U; 249 bool ShiftedFree = false, RunFree = false, UnsignedFree = false, 250 ZeroFree = false; 251 switch (Opcode) { 252 default: 253 return TTI::TCC_Free; 254 case Instruction::GetElementPtr: 255 // Always hoist the base address of a GetElementPtr. This prevents the 256 // creation of new constants for every base constant that gets constant 257 // folded with the offset. 258 if (Idx == 0) 259 return 2 * TTI::TCC_Basic; 260 return TTI::TCC_Free; 261 case Instruction::And: 262 RunFree = true; // (for the rotate-and-mask instructions) 263 LLVM_FALLTHROUGH; 264 case Instruction::Add: 265 case Instruction::Or: 266 case Instruction::Xor: 267 ShiftedFree = true; 268 LLVM_FALLTHROUGH; 269 case Instruction::Sub: 270 case Instruction::Mul: 271 case Instruction::Shl: 272 case Instruction::LShr: 273 case Instruction::AShr: 274 ImmIdx = 1; 275 break; 276 case Instruction::ICmp: 277 UnsignedFree = true; 278 ImmIdx = 1; 279 // Zero comparisons can use record-form instructions. 280 LLVM_FALLTHROUGH; 281 case Instruction::Select: 282 ZeroFree = true; 283 break; 284 case Instruction::PHI: 285 case Instruction::Call: 286 case Instruction::Ret: 287 case Instruction::Load: 288 case Instruction::Store: 289 break; 290 } 291 292 if (ZeroFree && Imm == 0) 293 return TTI::TCC_Free; 294 295 if (Idx == ImmIdx && Imm.getBitWidth() <= 64) { 296 if (isInt<16>(Imm.getSExtValue())) 297 return TTI::TCC_Free; 298 299 if (RunFree) { 300 if (Imm.getBitWidth() <= 32 && 301 (isShiftedMask_32(Imm.getZExtValue()) || 302 isShiftedMask_32(~Imm.getZExtValue()))) 303 return TTI::TCC_Free; 304 305 if (ST->isPPC64() && 306 (isShiftedMask_64(Imm.getZExtValue()) || 307 isShiftedMask_64(~Imm.getZExtValue()))) 308 return TTI::TCC_Free; 309 } 310 311 if (UnsignedFree && isUInt<16>(Imm.getZExtValue())) 312 return TTI::TCC_Free; 313 314 if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0) 315 return TTI::TCC_Free; 316 } 317 318 return PPCTTIImpl::getIntImmCost(Imm, Ty, CostKind); 319 } 320 321 // Check if the current Type is an MMA vector type. Valid MMA types are 322 // v256i1 and v512i1 respectively. 323 static bool isMMAType(Type *Ty) { 324 return Ty->isVectorTy() && (Ty->getScalarSizeInBits() == 1) && 325 (Ty->getPrimitiveSizeInBits() > 128); 326 } 327 328 InstructionCost PPCTTIImpl::getUserCost(const User *U, 329 ArrayRef<const Value *> Operands, 330 TTI::TargetCostKind CostKind) { 331 // We already implement getCastInstrCost and getMemoryOpCost where we perform 332 // the vector adjustment there. 333 if (isa<CastInst>(U) || isa<LoadInst>(U) || isa<StoreInst>(U)) 334 return BaseT::getUserCost(U, Operands, CostKind); 335 336 if (U->getType()->isVectorTy()) { 337 // Instructions that need to be split should cost more. 338 std::pair<InstructionCost, MVT> LT = 339 TLI->getTypeLegalizationCost(DL, U->getType()); 340 return LT.first * BaseT::getUserCost(U, Operands, CostKind); 341 } 342 343 return BaseT::getUserCost(U, Operands, CostKind); 344 } 345 346 // Determining the address of a TLS variable results in a function call in 347 // certain TLS models. 348 static bool memAddrUsesCTR(const Value *MemAddr, const PPCTargetMachine &TM, 349 SmallPtrSetImpl<const Value *> &Visited) { 350 // No need to traverse again if we already checked this operand. 351 if (!Visited.insert(MemAddr).second) 352 return false; 353 const auto *GV = dyn_cast<GlobalValue>(MemAddr); 354 if (!GV) { 355 // Recurse to check for constants that refer to TLS global variables. 356 if (const auto *CV = dyn_cast<Constant>(MemAddr)) 357 for (const auto &CO : CV->operands()) 358 if (memAddrUsesCTR(CO, TM, Visited)) 359 return true; 360 return false; 361 } 362 363 if (!GV->isThreadLocal()) 364 return false; 365 TLSModel::Model Model = TM.getTLSModel(GV); 366 return Model == TLSModel::GeneralDynamic || Model == TLSModel::LocalDynamic; 367 } 368 369 bool PPCTTIImpl::mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo, 370 SmallPtrSetImpl<const Value *> &Visited) { 371 const PPCTargetMachine &TM = ST->getTargetMachine(); 372 373 // Loop through the inline asm constraints and look for something that 374 // clobbers ctr. 375 auto asmClobbersCTR = [](InlineAsm *IA) { 376 InlineAsm::ConstraintInfoVector CIV = IA->ParseConstraints(); 377 for (const InlineAsm::ConstraintInfo &C : CIV) { 378 if (C.Type != InlineAsm::isInput) 379 for (const auto &Code : C.Codes) 380 if (StringRef(Code).equals_insensitive("{ctr}")) 381 return true; 382 } 383 return false; 384 }; 385 386 auto isLargeIntegerTy = [](bool Is32Bit, Type *Ty) { 387 if (IntegerType *ITy = dyn_cast<IntegerType>(Ty)) 388 return ITy->getBitWidth() > (Is32Bit ? 32U : 64U); 389 390 return false; 391 }; 392 393 auto supportedHalfPrecisionOp = [](Instruction *Inst) { 394 switch (Inst->getOpcode()) { 395 default: 396 return false; 397 case Instruction::FPTrunc: 398 case Instruction::FPExt: 399 case Instruction::Load: 400 case Instruction::Store: 401 case Instruction::FPToUI: 402 case Instruction::UIToFP: 403 case Instruction::FPToSI: 404 case Instruction::SIToFP: 405 return true; 406 } 407 }; 408 409 for (BasicBlock::iterator J = BB->begin(), JE = BB->end(); 410 J != JE; ++J) { 411 // There are no direct operations on half precision so assume that 412 // anything with that type requires a call except for a few select 413 // operations with Power9. 414 if (Instruction *CurrInst = dyn_cast<Instruction>(J)) { 415 for (const auto &Op : CurrInst->operands()) { 416 if (Op->getType()->getScalarType()->isHalfTy() || 417 CurrInst->getType()->getScalarType()->isHalfTy()) 418 return !(ST->isISA3_0() && supportedHalfPrecisionOp(CurrInst)); 419 } 420 } 421 if (CallInst *CI = dyn_cast<CallInst>(J)) { 422 // Inline ASM is okay, unless it clobbers the ctr register. 423 if (InlineAsm *IA = dyn_cast<InlineAsm>(CI->getCalledOperand())) { 424 if (asmClobbersCTR(IA)) 425 return true; 426 continue; 427 } 428 429 if (Function *F = CI->getCalledFunction()) { 430 // Most intrinsics don't become function calls, but some might. 431 // sin, cos, exp and log are always calls. 432 unsigned Opcode = 0; 433 if (F->getIntrinsicID() != Intrinsic::not_intrinsic) { 434 switch (F->getIntrinsicID()) { 435 default: continue; 436 // If we have a call to loop_decrement or set_loop_iterations, 437 // we're definitely using CTR. 438 case Intrinsic::set_loop_iterations: 439 case Intrinsic::loop_decrement: 440 return true; 441 442 // Binary operations on 128-bit value will use CTR. 443 case Intrinsic::experimental_constrained_fadd: 444 case Intrinsic::experimental_constrained_fsub: 445 case Intrinsic::experimental_constrained_fmul: 446 case Intrinsic::experimental_constrained_fdiv: 447 case Intrinsic::experimental_constrained_frem: 448 if (F->getType()->getScalarType()->isFP128Ty() || 449 F->getType()->getScalarType()->isPPC_FP128Ty()) 450 return true; 451 break; 452 453 case Intrinsic::experimental_constrained_fptosi: 454 case Intrinsic::experimental_constrained_fptoui: 455 case Intrinsic::experimental_constrained_sitofp: 456 case Intrinsic::experimental_constrained_uitofp: { 457 Type *SrcType = CI->getArgOperand(0)->getType()->getScalarType(); 458 Type *DstType = CI->getType()->getScalarType(); 459 if (SrcType->isPPC_FP128Ty() || DstType->isPPC_FP128Ty() || 460 isLargeIntegerTy(!TM.isPPC64(), SrcType) || 461 isLargeIntegerTy(!TM.isPPC64(), DstType)) 462 return true; 463 break; 464 } 465 466 // Exclude eh_sjlj_setjmp; we don't need to exclude eh_sjlj_longjmp 467 // because, although it does clobber the counter register, the 468 // control can't then return to inside the loop unless there is also 469 // an eh_sjlj_setjmp. 470 case Intrinsic::eh_sjlj_setjmp: 471 472 case Intrinsic::memcpy: 473 case Intrinsic::memmove: 474 case Intrinsic::memset: 475 case Intrinsic::powi: 476 case Intrinsic::log: 477 case Intrinsic::log2: 478 case Intrinsic::log10: 479 case Intrinsic::exp: 480 case Intrinsic::exp2: 481 case Intrinsic::pow: 482 case Intrinsic::sin: 483 case Intrinsic::cos: 484 case Intrinsic::experimental_constrained_powi: 485 case Intrinsic::experimental_constrained_log: 486 case Intrinsic::experimental_constrained_log2: 487 case Intrinsic::experimental_constrained_log10: 488 case Intrinsic::experimental_constrained_exp: 489 case Intrinsic::experimental_constrained_exp2: 490 case Intrinsic::experimental_constrained_pow: 491 case Intrinsic::experimental_constrained_sin: 492 case Intrinsic::experimental_constrained_cos: 493 return true; 494 case Intrinsic::copysign: 495 if (CI->getArgOperand(0)->getType()->getScalarType()-> 496 isPPC_FP128Ty()) 497 return true; 498 else 499 continue; // ISD::FCOPYSIGN is never a library call. 500 case Intrinsic::fmuladd: 501 case Intrinsic::fma: Opcode = ISD::FMA; break; 502 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; 503 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; 504 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; 505 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; 506 case Intrinsic::rint: Opcode = ISD::FRINT; break; 507 case Intrinsic::lrint: Opcode = ISD::LRINT; break; 508 case Intrinsic::llrint: Opcode = ISD::LLRINT; break; 509 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; 510 case Intrinsic::round: Opcode = ISD::FROUND; break; 511 case Intrinsic::lround: Opcode = ISD::LROUND; break; 512 case Intrinsic::llround: Opcode = ISD::LLROUND; break; 513 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break; 514 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; 515 case Intrinsic::experimental_constrained_fcmp: 516 Opcode = ISD::STRICT_FSETCC; 517 break; 518 case Intrinsic::experimental_constrained_fcmps: 519 Opcode = ISD::STRICT_FSETCCS; 520 break; 521 case Intrinsic::experimental_constrained_fma: 522 Opcode = ISD::STRICT_FMA; 523 break; 524 case Intrinsic::experimental_constrained_sqrt: 525 Opcode = ISD::STRICT_FSQRT; 526 break; 527 case Intrinsic::experimental_constrained_floor: 528 Opcode = ISD::STRICT_FFLOOR; 529 break; 530 case Intrinsic::experimental_constrained_ceil: 531 Opcode = ISD::STRICT_FCEIL; 532 break; 533 case Intrinsic::experimental_constrained_trunc: 534 Opcode = ISD::STRICT_FTRUNC; 535 break; 536 case Intrinsic::experimental_constrained_rint: 537 Opcode = ISD::STRICT_FRINT; 538 break; 539 case Intrinsic::experimental_constrained_lrint: 540 Opcode = ISD::STRICT_LRINT; 541 break; 542 case Intrinsic::experimental_constrained_llrint: 543 Opcode = ISD::STRICT_LLRINT; 544 break; 545 case Intrinsic::experimental_constrained_nearbyint: 546 Opcode = ISD::STRICT_FNEARBYINT; 547 break; 548 case Intrinsic::experimental_constrained_round: 549 Opcode = ISD::STRICT_FROUND; 550 break; 551 case Intrinsic::experimental_constrained_lround: 552 Opcode = ISD::STRICT_LROUND; 553 break; 554 case Intrinsic::experimental_constrained_llround: 555 Opcode = ISD::STRICT_LLROUND; 556 break; 557 case Intrinsic::experimental_constrained_minnum: 558 Opcode = ISD::STRICT_FMINNUM; 559 break; 560 case Intrinsic::experimental_constrained_maxnum: 561 Opcode = ISD::STRICT_FMAXNUM; 562 break; 563 case Intrinsic::umul_with_overflow: Opcode = ISD::UMULO; break; 564 case Intrinsic::smul_with_overflow: Opcode = ISD::SMULO; break; 565 } 566 } 567 568 // PowerPC does not use [US]DIVREM or other library calls for 569 // operations on regular types which are not otherwise library calls 570 // (i.e. soft float or atomics). If adapting for targets that do, 571 // additional care is required here. 572 573 LibFunc Func; 574 if (!F->hasLocalLinkage() && F->hasName() && LibInfo && 575 LibInfo->getLibFunc(F->getName(), Func) && 576 LibInfo->hasOptimizedCodeGen(Func)) { 577 // Non-read-only functions are never treated as intrinsics. 578 if (!CI->onlyReadsMemory()) 579 return true; 580 581 // Conversion happens only for FP calls. 582 if (!CI->getArgOperand(0)->getType()->isFloatingPointTy()) 583 return true; 584 585 switch (Func) { 586 default: return true; 587 case LibFunc_copysign: 588 case LibFunc_copysignf: 589 continue; // ISD::FCOPYSIGN is never a library call. 590 case LibFunc_copysignl: 591 return true; 592 case LibFunc_fabs: 593 case LibFunc_fabsf: 594 case LibFunc_fabsl: 595 continue; // ISD::FABS is never a library call. 596 case LibFunc_sqrt: 597 case LibFunc_sqrtf: 598 case LibFunc_sqrtl: 599 Opcode = ISD::FSQRT; break; 600 case LibFunc_floor: 601 case LibFunc_floorf: 602 case LibFunc_floorl: 603 Opcode = ISD::FFLOOR; break; 604 case LibFunc_nearbyint: 605 case LibFunc_nearbyintf: 606 case LibFunc_nearbyintl: 607 Opcode = ISD::FNEARBYINT; break; 608 case LibFunc_ceil: 609 case LibFunc_ceilf: 610 case LibFunc_ceill: 611 Opcode = ISD::FCEIL; break; 612 case LibFunc_rint: 613 case LibFunc_rintf: 614 case LibFunc_rintl: 615 Opcode = ISD::FRINT; break; 616 case LibFunc_round: 617 case LibFunc_roundf: 618 case LibFunc_roundl: 619 Opcode = ISD::FROUND; break; 620 case LibFunc_trunc: 621 case LibFunc_truncf: 622 case LibFunc_truncl: 623 Opcode = ISD::FTRUNC; break; 624 case LibFunc_fmin: 625 case LibFunc_fminf: 626 case LibFunc_fminl: 627 Opcode = ISD::FMINNUM; break; 628 case LibFunc_fmax: 629 case LibFunc_fmaxf: 630 case LibFunc_fmaxl: 631 Opcode = ISD::FMAXNUM; break; 632 } 633 } 634 635 if (Opcode) { 636 EVT EVTy = 637 TLI->getValueType(DL, CI->getArgOperand(0)->getType(), true); 638 639 if (EVTy == MVT::Other) 640 return true; 641 642 if (TLI->isOperationLegalOrCustom(Opcode, EVTy)) 643 continue; 644 else if (EVTy.isVector() && 645 TLI->isOperationLegalOrCustom(Opcode, EVTy.getScalarType())) 646 continue; 647 648 return true; 649 } 650 } 651 652 return true; 653 } else if ((J->getType()->getScalarType()->isFP128Ty() || 654 J->getType()->getScalarType()->isPPC_FP128Ty())) { 655 // Most operations on f128 or ppc_f128 values become calls. 656 return true; 657 } else if (isa<FCmpInst>(J) && 658 J->getOperand(0)->getType()->getScalarType()->isFP128Ty()) { 659 return true; 660 } else if ((isa<FPTruncInst>(J) || isa<FPExtInst>(J)) && 661 (cast<CastInst>(J)->getSrcTy()->getScalarType()->isFP128Ty() || 662 cast<CastInst>(J)->getDestTy()->getScalarType()->isFP128Ty())) { 663 return true; 664 } else if (isa<UIToFPInst>(J) || isa<SIToFPInst>(J) || 665 isa<FPToUIInst>(J) || isa<FPToSIInst>(J)) { 666 CastInst *CI = cast<CastInst>(J); 667 if (CI->getSrcTy()->getScalarType()->isPPC_FP128Ty() || 668 CI->getDestTy()->getScalarType()->isPPC_FP128Ty() || 669 isLargeIntegerTy(!TM.isPPC64(), CI->getSrcTy()->getScalarType()) || 670 isLargeIntegerTy(!TM.isPPC64(), CI->getDestTy()->getScalarType())) 671 return true; 672 } else if (isLargeIntegerTy(!TM.isPPC64(), 673 J->getType()->getScalarType()) && 674 (J->getOpcode() == Instruction::UDiv || 675 J->getOpcode() == Instruction::SDiv || 676 J->getOpcode() == Instruction::URem || 677 J->getOpcode() == Instruction::SRem)) { 678 return true; 679 } else if (!TM.isPPC64() && 680 isLargeIntegerTy(false, J->getType()->getScalarType()) && 681 (J->getOpcode() == Instruction::Shl || 682 J->getOpcode() == Instruction::AShr || 683 J->getOpcode() == Instruction::LShr)) { 684 // Only on PPC32, for 128-bit integers (specifically not 64-bit 685 // integers), these might be runtime calls. 686 return true; 687 } else if (isa<IndirectBrInst>(J) || isa<InvokeInst>(J)) { 688 // On PowerPC, indirect jumps use the counter register. 689 return true; 690 } else if (SwitchInst *SI = dyn_cast<SwitchInst>(J)) { 691 if (SI->getNumCases() + 1 >= (unsigned)TLI->getMinimumJumpTableEntries()) 692 return true; 693 } 694 695 // FREM is always a call. 696 if (J->getOpcode() == Instruction::FRem) 697 return true; 698 699 if (ST->useSoftFloat()) { 700 switch(J->getOpcode()) { 701 case Instruction::FAdd: 702 case Instruction::FSub: 703 case Instruction::FMul: 704 case Instruction::FDiv: 705 case Instruction::FPTrunc: 706 case Instruction::FPExt: 707 case Instruction::FPToUI: 708 case Instruction::FPToSI: 709 case Instruction::UIToFP: 710 case Instruction::SIToFP: 711 case Instruction::FCmp: 712 return true; 713 } 714 } 715 716 for (Value *Operand : J->operands()) 717 if (memAddrUsesCTR(Operand, TM, Visited)) 718 return true; 719 } 720 721 return false; 722 } 723 724 bool PPCTTIImpl::isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, 725 AssumptionCache &AC, 726 TargetLibraryInfo *LibInfo, 727 HardwareLoopInfo &HWLoopInfo) { 728 const PPCTargetMachine &TM = ST->getTargetMachine(); 729 TargetSchedModel SchedModel; 730 SchedModel.init(ST); 731 732 // Do not convert small short loops to CTR loop. 733 unsigned ConstTripCount = SE.getSmallConstantTripCount(L); 734 if (ConstTripCount && ConstTripCount < SmallCTRLoopThreshold) { 735 SmallPtrSet<const Value *, 32> EphValues; 736 CodeMetrics::collectEphemeralValues(L, &AC, EphValues); 737 CodeMetrics Metrics; 738 for (BasicBlock *BB : L->blocks()) 739 Metrics.analyzeBasicBlock(BB, *this, EphValues); 740 // 6 is an approximate latency for the mtctr instruction. 741 if (Metrics.NumInsts <= (6 * SchedModel.getIssueWidth())) 742 return false; 743 } 744 745 // We don't want to spill/restore the counter register, and so we don't 746 // want to use the counter register if the loop contains calls. 747 SmallPtrSet<const Value *, 4> Visited; 748 for (Loop::block_iterator I = L->block_begin(), IE = L->block_end(); 749 I != IE; ++I) 750 if (mightUseCTR(*I, LibInfo, Visited)) 751 return false; 752 753 SmallVector<BasicBlock*, 4> ExitingBlocks; 754 L->getExitingBlocks(ExitingBlocks); 755 756 // If there is an exit edge known to be frequently taken, 757 // we should not transform this loop. 758 for (auto &BB : ExitingBlocks) { 759 Instruction *TI = BB->getTerminator(); 760 if (!TI) continue; 761 762 if (BranchInst *BI = dyn_cast<BranchInst>(TI)) { 763 uint64_t TrueWeight = 0, FalseWeight = 0; 764 if (!BI->isConditional() || 765 !BI->extractProfMetadata(TrueWeight, FalseWeight)) 766 continue; 767 768 // If the exit path is more frequent than the loop path, 769 // we return here without further analysis for this loop. 770 bool TrueIsExit = !L->contains(BI->getSuccessor(0)); 771 if (( TrueIsExit && FalseWeight < TrueWeight) || 772 (!TrueIsExit && FalseWeight > TrueWeight)) 773 return false; 774 } 775 } 776 777 // If an exit block has a PHI that accesses a TLS variable as one of the 778 // incoming values from the loop, we cannot produce a CTR loop because the 779 // address for that value will be computed in the loop. 780 SmallVector<BasicBlock *, 4> ExitBlocks; 781 L->getExitBlocks(ExitBlocks); 782 for (auto &BB : ExitBlocks) { 783 for (auto &PHI : BB->phis()) { 784 for (int Idx = 0, EndIdx = PHI.getNumIncomingValues(); Idx < EndIdx; 785 Idx++) { 786 const BasicBlock *IncomingBB = PHI.getIncomingBlock(Idx); 787 const Value *IncomingValue = PHI.getIncomingValue(Idx); 788 if (L->contains(IncomingBB) && 789 memAddrUsesCTR(IncomingValue, TM, Visited)) 790 return false; 791 } 792 } 793 } 794 795 LLVMContext &C = L->getHeader()->getContext(); 796 HWLoopInfo.CountType = TM.isPPC64() ? 797 Type::getInt64Ty(C) : Type::getInt32Ty(C); 798 HWLoopInfo.LoopDecrement = ConstantInt::get(HWLoopInfo.CountType, 1); 799 return true; 800 } 801 802 void PPCTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, 803 TTI::UnrollingPreferences &UP, 804 OptimizationRemarkEmitter *ORE) { 805 if (ST->getCPUDirective() == PPC::DIR_A2) { 806 // The A2 is in-order with a deep pipeline, and concatenation unrolling 807 // helps expose latency-hiding opportunities to the instruction scheduler. 808 UP.Partial = UP.Runtime = true; 809 810 // We unroll a lot on the A2 (hundreds of instructions), and the benefits 811 // often outweigh the cost of a division to compute the trip count. 812 UP.AllowExpensiveTripCount = true; 813 } 814 815 BaseT::getUnrollingPreferences(L, SE, UP, ORE); 816 } 817 818 void PPCTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE, 819 TTI::PeelingPreferences &PP) { 820 BaseT::getPeelingPreferences(L, SE, PP); 821 } 822 // This function returns true to allow using coldcc calling convention. 823 // Returning true results in coldcc being used for functions which are cold at 824 // all call sites when the callers of the functions are not calling any other 825 // non coldcc functions. 826 bool PPCTTIImpl::useColdCCForColdCall(Function &F) { 827 return EnablePPCColdCC; 828 } 829 830 bool PPCTTIImpl::enableAggressiveInterleaving(bool LoopHasReductions) { 831 // On the A2, always unroll aggressively. 832 if (ST->getCPUDirective() == PPC::DIR_A2) 833 return true; 834 835 return LoopHasReductions; 836 } 837 838 PPCTTIImpl::TTI::MemCmpExpansionOptions 839 PPCTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 840 TTI::MemCmpExpansionOptions Options; 841 Options.LoadSizes = {8, 4, 2, 1}; 842 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 843 return Options; 844 } 845 846 bool PPCTTIImpl::enableInterleavedAccessVectorization() { 847 return true; 848 } 849 850 unsigned PPCTTIImpl::getNumberOfRegisters(unsigned ClassID) const { 851 assert(ClassID == GPRRC || ClassID == FPRRC || 852 ClassID == VRRC || ClassID == VSXRC); 853 if (ST->hasVSX()) { 854 assert(ClassID == GPRRC || ClassID == VSXRC || ClassID == VRRC); 855 return ClassID == VSXRC ? 64 : 32; 856 } 857 assert(ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC); 858 return 32; 859 } 860 861 unsigned PPCTTIImpl::getRegisterClassForType(bool Vector, Type *Ty) const { 862 if (Vector) 863 return ST->hasVSX() ? VSXRC : VRRC; 864 else if (Ty && (Ty->getScalarType()->isFloatTy() || 865 Ty->getScalarType()->isDoubleTy())) 866 return ST->hasVSX() ? VSXRC : FPRRC; 867 else if (Ty && (Ty->getScalarType()->isFP128Ty() || 868 Ty->getScalarType()->isPPC_FP128Ty())) 869 return VRRC; 870 else if (Ty && Ty->getScalarType()->isHalfTy()) 871 return VSXRC; 872 else 873 return GPRRC; 874 } 875 876 const char* PPCTTIImpl::getRegisterClassName(unsigned ClassID) const { 877 878 switch (ClassID) { 879 default: 880 llvm_unreachable("unknown register class"); 881 return "PPC::unknown register class"; 882 case GPRRC: return "PPC::GPRRC"; 883 case FPRRC: return "PPC::FPRRC"; 884 case VRRC: return "PPC::VRRC"; 885 case VSXRC: return "PPC::VSXRC"; 886 } 887 } 888 889 TypeSize 890 PPCTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 891 switch (K) { 892 case TargetTransformInfo::RGK_Scalar: 893 return TypeSize::getFixed(ST->isPPC64() ? 64 : 32); 894 case TargetTransformInfo::RGK_FixedWidthVector: 895 return TypeSize::getFixed(ST->hasAltivec() ? 128 : 0); 896 case TargetTransformInfo::RGK_ScalableVector: 897 return TypeSize::getScalable(0); 898 } 899 900 llvm_unreachable("Unsupported register kind"); 901 } 902 903 unsigned PPCTTIImpl::getCacheLineSize() const { 904 // Check first if the user specified a custom line size. 905 if (CacheLineSize.getNumOccurrences() > 0) 906 return CacheLineSize; 907 908 // Starting with P7 we have a cache line size of 128. 909 unsigned Directive = ST->getCPUDirective(); 910 // Assume that Future CPU has the same cache line size as the others. 911 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 || 912 Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 || 913 Directive == PPC::DIR_PWR_FUTURE) 914 return 128; 915 916 // On other processors return a default of 64 bytes. 917 return 64; 918 } 919 920 unsigned PPCTTIImpl::getPrefetchDistance() const { 921 return 300; 922 } 923 924 unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) { 925 unsigned Directive = ST->getCPUDirective(); 926 // The 440 has no SIMD support, but floating-point instructions 927 // have a 5-cycle latency, so unroll by 5x for latency hiding. 928 if (Directive == PPC::DIR_440) 929 return 5; 930 931 // The A2 has no SIMD support, but floating-point instructions 932 // have a 6-cycle latency, so unroll by 6x for latency hiding. 933 if (Directive == PPC::DIR_A2) 934 return 6; 935 936 // FIXME: For lack of any better information, do no harm... 937 if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) 938 return 1; 939 940 // For P7 and P8, floating-point instructions have a 6-cycle latency and 941 // there are two execution units, so unroll by 12x for latency hiding. 942 // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready 943 // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready 944 // Assume that future is the same as the others. 945 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 || 946 Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 || 947 Directive == PPC::DIR_PWR_FUTURE) 948 return 12; 949 950 // For most things, modern systems have two execution units (and 951 // out-of-order execution). 952 return 2; 953 } 954 955 // Returns a cost adjustment factor to adjust the cost of vector instructions 956 // on targets which there is overlap between the vector and scalar units, 957 // thereby reducing the overall throughput of vector code wrt. scalar code. 958 // An invalid instruction cost is returned if the type is an MMA vector type. 959 InstructionCost PPCTTIImpl::vectorCostAdjustmentFactor(unsigned Opcode, 960 Type *Ty1, Type *Ty2) { 961 // If the vector type is of an MMA type (v256i1, v512i1), an invalid 962 // instruction cost is returned. This is to signify to other cost computing 963 // functions to return the maximum instruction cost in order to prevent any 964 // opportunities for the optimizer to produce MMA types within the IR. 965 if (isMMAType(Ty1)) 966 return InstructionCost::getInvalid(); 967 968 if (!ST->vectorsUseTwoUnits() || !Ty1->isVectorTy()) 969 return InstructionCost(1); 970 971 std::pair<InstructionCost, MVT> LT1 = TLI->getTypeLegalizationCost(DL, Ty1); 972 // If type legalization involves splitting the vector, we don't want to 973 // double the cost at every step - only the last step. 974 if (LT1.first != 1 || !LT1.second.isVector()) 975 return InstructionCost(1); 976 977 int ISD = TLI->InstructionOpcodeToISD(Opcode); 978 if (TLI->isOperationExpand(ISD, LT1.second)) 979 return InstructionCost(1); 980 981 if (Ty2) { 982 std::pair<InstructionCost, MVT> LT2 = TLI->getTypeLegalizationCost(DL, Ty2); 983 if (LT2.first != 1 || !LT2.second.isVector()) 984 return InstructionCost(1); 985 } 986 987 return InstructionCost(2); 988 } 989 990 InstructionCost PPCTTIImpl::getArithmeticInstrCost( 991 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 992 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 993 TTI::OperandValueProperties Opd1PropInfo, 994 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 995 const Instruction *CxtI) { 996 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode"); 997 998 InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Ty, nullptr); 999 if (!CostFactor.isValid()) 1000 return InstructionCost::getMax(); 1001 1002 // TODO: Handle more cost kinds. 1003 if (CostKind != TTI::TCK_RecipThroughput) 1004 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 1005 Op2Info, Opd1PropInfo, 1006 Opd2PropInfo, Args, CxtI); 1007 1008 // Fallback to the default implementation. 1009 InstructionCost Cost = BaseT::getArithmeticInstrCost( 1010 Opcode, Ty, CostKind, Op1Info, Op2Info, Opd1PropInfo, Opd2PropInfo); 1011 return Cost * CostFactor; 1012 } 1013 1014 InstructionCost PPCTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, 1015 ArrayRef<int> Mask, int Index, 1016 Type *SubTp) { 1017 1018 InstructionCost CostFactor = 1019 vectorCostAdjustmentFactor(Instruction::ShuffleVector, Tp, nullptr); 1020 if (!CostFactor.isValid()) 1021 return InstructionCost::getMax(); 1022 1023 // Legalize the type. 1024 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 1025 1026 // PPC, for both Altivec/VSX, support cheap arbitrary permutations 1027 // (at least in the sense that there need only be one non-loop-invariant 1028 // instruction). We need one such shuffle instruction for each actual 1029 // register (this is not true for arbitrary shuffles, but is true for the 1030 // structured types of shuffles covered by TTI::ShuffleKind). 1031 return LT.first * CostFactor; 1032 } 1033 1034 InstructionCost PPCTTIImpl::getCFInstrCost(unsigned Opcode, 1035 TTI::TargetCostKind CostKind, 1036 const Instruction *I) { 1037 if (CostKind != TTI::TCK_RecipThroughput) 1038 return Opcode == Instruction::PHI ? 0 : 1; 1039 // Branches are assumed to be predicted. 1040 return 0; 1041 } 1042 1043 InstructionCost PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1044 Type *Src, 1045 TTI::CastContextHint CCH, 1046 TTI::TargetCostKind CostKind, 1047 const Instruction *I) { 1048 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode"); 1049 1050 InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Dst, Src); 1051 if (!CostFactor.isValid()) 1052 return InstructionCost::getMax(); 1053 1054 InstructionCost Cost = 1055 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I); 1056 Cost *= CostFactor; 1057 // TODO: Allow non-throughput costs that aren't binary. 1058 if (CostKind != TTI::TCK_RecipThroughput) 1059 return Cost == 0 ? 0 : 1; 1060 return Cost; 1061 } 1062 1063 InstructionCost PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 1064 Type *CondTy, 1065 CmpInst::Predicate VecPred, 1066 TTI::TargetCostKind CostKind, 1067 const Instruction *I) { 1068 InstructionCost CostFactor = 1069 vectorCostAdjustmentFactor(Opcode, ValTy, nullptr); 1070 if (!CostFactor.isValid()) 1071 return InstructionCost::getMax(); 1072 1073 InstructionCost Cost = 1074 BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 1075 // TODO: Handle other cost kinds. 1076 if (CostKind != TTI::TCK_RecipThroughput) 1077 return Cost; 1078 return Cost * CostFactor; 1079 } 1080 1081 InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 1082 unsigned Index) { 1083 assert(Val->isVectorTy() && "This must be a vector type"); 1084 1085 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1086 assert(ISD && "Invalid opcode"); 1087 1088 InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Val, nullptr); 1089 if (!CostFactor.isValid()) 1090 return InstructionCost::getMax(); 1091 1092 InstructionCost Cost = BaseT::getVectorInstrCost(Opcode, Val, Index); 1093 Cost *= CostFactor; 1094 1095 if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) { 1096 // Double-precision scalars are already located in index #0 (or #1 if LE). 1097 if (ISD == ISD::EXTRACT_VECTOR_ELT && 1098 Index == (ST->isLittleEndian() ? 1 : 0)) 1099 return 0; 1100 1101 return Cost; 1102 1103 } else if (Val->getScalarType()->isIntegerTy() && Index != -1U) { 1104 if (ST->hasP9Altivec()) { 1105 if (ISD == ISD::INSERT_VECTOR_ELT) 1106 // A move-to VSR and a permute/insert. Assume vector operation cost 1107 // for both (cost will be 2x on P9). 1108 return 2 * CostFactor; 1109 1110 // It's an extract. Maybe we can do a cheap move-from VSR. 1111 unsigned EltSize = Val->getScalarSizeInBits(); 1112 if (EltSize == 64) { 1113 unsigned MfvsrdIndex = ST->isLittleEndian() ? 1 : 0; 1114 if (Index == MfvsrdIndex) 1115 return 1; 1116 } else if (EltSize == 32) { 1117 unsigned MfvsrwzIndex = ST->isLittleEndian() ? 2 : 1; 1118 if (Index == MfvsrwzIndex) 1119 return 1; 1120 } 1121 1122 // We need a vector extract (or mfvsrld). Assume vector operation cost. 1123 // The cost of the load constant for a vector extract is disregarded 1124 // (invariant, easily schedulable). 1125 return CostFactor; 1126 1127 } else if (ST->hasDirectMove()) 1128 // Assume permute has standard cost. 1129 // Assume move-to/move-from VSR have 2x standard cost. 1130 return 3; 1131 } 1132 1133 // Estimated cost of a load-hit-store delay. This was obtained 1134 // experimentally as a minimum needed to prevent unprofitable 1135 // vectorization for the paq8p benchmark. It may need to be 1136 // raised further if other unprofitable cases remain. 1137 unsigned LHSPenalty = 2; 1138 if (ISD == ISD::INSERT_VECTOR_ELT) 1139 LHSPenalty += 7; 1140 1141 // Vector element insert/extract with Altivec is very expensive, 1142 // because they require store and reload with the attendant 1143 // processor stall for load-hit-store. Until VSX is available, 1144 // these need to be estimated as very costly. 1145 if (ISD == ISD::EXTRACT_VECTOR_ELT || 1146 ISD == ISD::INSERT_VECTOR_ELT) 1147 return LHSPenalty + Cost; 1148 1149 return Cost; 1150 } 1151 1152 InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 1153 MaybeAlign Alignment, 1154 unsigned AddressSpace, 1155 TTI::TargetCostKind CostKind, 1156 const Instruction *I) { 1157 1158 InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Src, nullptr); 1159 if (!CostFactor.isValid()) 1160 return InstructionCost::getMax(); 1161 1162 if (TLI->getValueType(DL, Src, true) == MVT::Other) 1163 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 1164 CostKind); 1165 // Legalize the type. 1166 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 1167 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 1168 "Invalid Opcode"); 1169 1170 InstructionCost Cost = 1171 BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind); 1172 // TODO: Handle other cost kinds. 1173 if (CostKind != TTI::TCK_RecipThroughput) 1174 return Cost; 1175 1176 Cost *= CostFactor; 1177 1178 bool IsAltivecType = ST->hasAltivec() && 1179 (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 || 1180 LT.second == MVT::v4i32 || LT.second == MVT::v4f32); 1181 bool IsVSXType = ST->hasVSX() && 1182 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64); 1183 1184 // VSX has 32b/64b load instructions. Legalization can handle loading of 1185 // 32b/64b to VSR correctly and cheaply. But BaseT::getMemoryOpCost and 1186 // PPCTargetLowering can't compute the cost appropriately. So here we 1187 // explicitly check this case. 1188 unsigned MemBytes = Src->getPrimitiveSizeInBits(); 1189 if (Opcode == Instruction::Load && ST->hasVSX() && IsAltivecType && 1190 (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32))) 1191 return 1; 1192 1193 // Aligned loads and stores are easy. 1194 unsigned SrcBytes = LT.second.getStoreSize(); 1195 if (!SrcBytes || !Alignment || *Alignment >= SrcBytes) 1196 return Cost; 1197 1198 // If we can use the permutation-based load sequence, then this is also 1199 // relatively cheap (not counting loop-invariant instructions): one load plus 1200 // one permute (the last load in a series has extra cost, but we're 1201 // neglecting that here). Note that on the P7, we could do unaligned loads 1202 // for Altivec types using the VSX instructions, but that's more expensive 1203 // than using the permutation-based load sequence. On the P8, that's no 1204 // longer true. 1205 if (Opcode == Instruction::Load && (!ST->hasP8Vector() && IsAltivecType) && 1206 *Alignment >= LT.second.getScalarType().getStoreSize()) 1207 return Cost + LT.first; // Add the cost of the permutations. 1208 1209 // For VSX, we can do unaligned loads and stores on Altivec/VSX types. On the 1210 // P7, unaligned vector loads are more expensive than the permutation-based 1211 // load sequence, so that might be used instead, but regardless, the net cost 1212 // is about the same (not counting loop-invariant instructions). 1213 if (IsVSXType || (ST->hasVSX() && IsAltivecType)) 1214 return Cost; 1215 1216 // Newer PPC supports unaligned memory access. 1217 if (TLI->allowsMisalignedMemoryAccesses(LT.second, 0)) 1218 return Cost; 1219 1220 // PPC in general does not support unaligned loads and stores. They'll need 1221 // to be decomposed based on the alignment factor. 1222 1223 // Add the cost of each scalar load or store. 1224 assert(Alignment); 1225 Cost += LT.first * ((SrcBytes / Alignment->value()) - 1); 1226 1227 // For a vector type, there is also scalarization overhead (only for 1228 // stores, loads are expanded using the vector-load + permutation sequence, 1229 // which is much less expensive). 1230 if (Src->isVectorTy() && Opcode == Instruction::Store) 1231 for (int i = 0, e = cast<FixedVectorType>(Src)->getNumElements(); i < e; 1232 ++i) 1233 Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i); 1234 1235 return Cost; 1236 } 1237 1238 InstructionCost PPCTTIImpl::getInterleavedMemoryOpCost( 1239 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 1240 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 1241 bool UseMaskForCond, bool UseMaskForGaps) { 1242 InstructionCost CostFactor = 1243 vectorCostAdjustmentFactor(Opcode, VecTy, nullptr); 1244 if (!CostFactor.isValid()) 1245 return InstructionCost::getMax(); 1246 1247 if (UseMaskForCond || UseMaskForGaps) 1248 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 1249 Alignment, AddressSpace, CostKind, 1250 UseMaskForCond, UseMaskForGaps); 1251 1252 assert(isa<VectorType>(VecTy) && 1253 "Expect a vector type for interleaved memory op"); 1254 1255 // Legalize the type. 1256 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, VecTy); 1257 1258 // Firstly, the cost of load/store operation. 1259 InstructionCost Cost = getMemoryOpCost(Opcode, VecTy, MaybeAlign(Alignment), 1260 AddressSpace, CostKind); 1261 1262 // PPC, for both Altivec/VSX, support cheap arbitrary permutations 1263 // (at least in the sense that there need only be one non-loop-invariant 1264 // instruction). For each result vector, we need one shuffle per incoming 1265 // vector (except that the first shuffle can take two incoming vectors 1266 // because it does not need to take itself). 1267 Cost += Factor*(LT.first-1); 1268 1269 return Cost; 1270 } 1271 1272 InstructionCost 1273 PPCTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 1274 TTI::TargetCostKind CostKind) { 1275 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 1276 } 1277 1278 bool PPCTTIImpl::areTypesABICompatible(const Function *Caller, 1279 const Function *Callee, 1280 const ArrayRef<Type *> &Types) const { 1281 1282 // We need to ensure that argument promotion does not 1283 // attempt to promote pointers to MMA types (__vector_pair 1284 // and __vector_quad) since these types explicitly cannot be 1285 // passed as arguments. Both of these types are larger than 1286 // the 128-bit Altivec vectors and have a scalar size of 1 bit. 1287 if (!BaseT::areTypesABICompatible(Caller, Callee, Types)) 1288 return false; 1289 1290 return llvm::none_of(Types, [](Type *Ty) { 1291 if (Ty->isSized()) 1292 return Ty->isIntOrIntVectorTy(1) && Ty->getPrimitiveSizeInBits() > 128; 1293 return false; 1294 }); 1295 } 1296 1297 bool PPCTTIImpl::canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, 1298 LoopInfo *LI, DominatorTree *DT, 1299 AssumptionCache *AC, TargetLibraryInfo *LibInfo) { 1300 // Process nested loops first. 1301 for (Loop *I : *L) 1302 if (canSaveCmp(I, BI, SE, LI, DT, AC, LibInfo)) 1303 return false; // Stop search. 1304 1305 HardwareLoopInfo HWLoopInfo(L); 1306 1307 if (!HWLoopInfo.canAnalyze(*LI)) 1308 return false; 1309 1310 if (!isHardwareLoopProfitable(L, *SE, *AC, LibInfo, HWLoopInfo)) 1311 return false; 1312 1313 if (!HWLoopInfo.isHardwareLoopCandidate(*SE, *LI, *DT)) 1314 return false; 1315 1316 *BI = HWLoopInfo.ExitBranch; 1317 return true; 1318 } 1319 1320 bool PPCTTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 1321 TargetTransformInfo::LSRCost &C2) { 1322 // PowerPC default behaviour here is "instruction number 1st priority". 1323 // If LsrNoInsnsCost is set, call default implementation. 1324 if (!LsrNoInsnsCost) 1325 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, 1326 C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 1327 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, 1328 C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost); 1329 else 1330 return TargetTransformInfoImplBase::isLSRCostLess(C1, C2); 1331 } 1332 1333 bool PPCTTIImpl::isNumRegsMajorCostOfLSR() { 1334 return false; 1335 } 1336 1337 bool PPCTTIImpl::shouldBuildRelLookupTables() const { 1338 const PPCTargetMachine &TM = ST->getTargetMachine(); 1339 // XCOFF hasn't implemented lowerRelativeReference, disable non-ELF for now. 1340 if (!TM.isELFv2ABI()) 1341 return false; 1342 return BaseT::shouldBuildRelLookupTables(); 1343 } 1344 1345 bool PPCTTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst, 1346 MemIntrinsicInfo &Info) { 1347 switch (Inst->getIntrinsicID()) { 1348 case Intrinsic::ppc_altivec_lvx: 1349 case Intrinsic::ppc_altivec_lvxl: 1350 case Intrinsic::ppc_altivec_lvebx: 1351 case Intrinsic::ppc_altivec_lvehx: 1352 case Intrinsic::ppc_altivec_lvewx: 1353 case Intrinsic::ppc_vsx_lxvd2x: 1354 case Intrinsic::ppc_vsx_lxvw4x: 1355 case Intrinsic::ppc_vsx_lxvd2x_be: 1356 case Intrinsic::ppc_vsx_lxvw4x_be: 1357 case Intrinsic::ppc_vsx_lxvl: 1358 case Intrinsic::ppc_vsx_lxvll: 1359 case Intrinsic::ppc_vsx_lxvp: { 1360 Info.PtrVal = Inst->getArgOperand(0); 1361 Info.ReadMem = true; 1362 Info.WriteMem = false; 1363 return true; 1364 } 1365 case Intrinsic::ppc_altivec_stvx: 1366 case Intrinsic::ppc_altivec_stvxl: 1367 case Intrinsic::ppc_altivec_stvebx: 1368 case Intrinsic::ppc_altivec_stvehx: 1369 case Intrinsic::ppc_altivec_stvewx: 1370 case Intrinsic::ppc_vsx_stxvd2x: 1371 case Intrinsic::ppc_vsx_stxvw4x: 1372 case Intrinsic::ppc_vsx_stxvd2x_be: 1373 case Intrinsic::ppc_vsx_stxvw4x_be: 1374 case Intrinsic::ppc_vsx_stxvl: 1375 case Intrinsic::ppc_vsx_stxvll: 1376 case Intrinsic::ppc_vsx_stxvp: { 1377 Info.PtrVal = Inst->getArgOperand(1); 1378 Info.ReadMem = false; 1379 Info.WriteMem = true; 1380 return true; 1381 } 1382 default: 1383 break; 1384 } 1385 1386 return false; 1387 } 1388 1389 bool PPCTTIImpl::hasActiveVectorLength(unsigned Opcode, Type *DataType, 1390 Align Alignment) const { 1391 // Only load and stores instructions can have variable vector length on Power. 1392 if (Opcode != Instruction::Load && Opcode != Instruction::Store) 1393 return false; 1394 // Loads/stores with length instructions use bits 0-7 of the GPR operand and 1395 // therefore cannot be used in 32-bit mode. 1396 if ((!ST->hasP9Vector() && !ST->hasP10Vector()) || !ST->isPPC64()) 1397 return false; 1398 if (isa<FixedVectorType>(DataType)) { 1399 unsigned VecWidth = DataType->getPrimitiveSizeInBits(); 1400 return VecWidth == 128; 1401 } 1402 Type *ScalarTy = DataType->getScalarType(); 1403 1404 if (ScalarTy->isPointerTy()) 1405 return true; 1406 1407 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 1408 return true; 1409 1410 if (!ScalarTy->isIntegerTy()) 1411 return false; 1412 1413 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 1414 return IntWidth == 8 || IntWidth == 16 || IntWidth == 32 || IntWidth == 64; 1415 } 1416 1417 InstructionCost PPCTTIImpl::getVPMemoryOpCost(unsigned Opcode, Type *Src, 1418 Align Alignment, 1419 unsigned AddressSpace, 1420 TTI::TargetCostKind CostKind, 1421 const Instruction *I) { 1422 InstructionCost Cost = BaseT::getVPMemoryOpCost(Opcode, Src, Alignment, 1423 AddressSpace, CostKind, I); 1424 if (TLI->getValueType(DL, Src, true) == MVT::Other) 1425 return Cost; 1426 // TODO: Handle other cost kinds. 1427 if (CostKind != TTI::TCK_RecipThroughput) 1428 return Cost; 1429 1430 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 1431 "Invalid Opcode"); 1432 1433 auto *SrcVTy = dyn_cast<FixedVectorType>(Src); 1434 assert(SrcVTy && "Expected a vector type for VP memory operations"); 1435 1436 if (hasActiveVectorLength(Opcode, Src, Alignment)) { 1437 std::pair<InstructionCost, MVT> LT = 1438 TLI->getTypeLegalizationCost(DL, SrcVTy); 1439 1440 InstructionCost CostFactor = 1441 vectorCostAdjustmentFactor(Opcode, Src, nullptr); 1442 if (!CostFactor.isValid()) 1443 return InstructionCost::getMax(); 1444 1445 InstructionCost Cost = LT.first * CostFactor; 1446 assert(Cost.isValid() && "Expected valid cost"); 1447 1448 // On P9 but not on P10, if the op is misaligned then it will cause a 1449 // pipeline flush. Otherwise the VSX masked memops cost the same as unmasked 1450 // ones. 1451 const Align DesiredAlignment(16); 1452 if (Alignment >= DesiredAlignment || ST->getCPUDirective() != PPC::DIR_PWR9) 1453 return Cost; 1454 1455 // Since alignment may be under estimated, we try to compute the probability 1456 // that the actual address is aligned to the desired boundary. For example 1457 // an 8-byte aligned load is assumed to be actually 16-byte aligned half the 1458 // time, while a 4-byte aligned load has a 25% chance of being 16-byte 1459 // aligned. 1460 float AlignmentProb = ((float)Alignment.value()) / DesiredAlignment.value(); 1461 float MisalignmentProb = 1.0 - AlignmentProb; 1462 return (MisalignmentProb * P9PipelineFlushEstimate) + 1463 (AlignmentProb * *Cost.getValue()); 1464 } 1465 1466 // Usually we should not get to this point, but the following is an attempt to 1467 // model the cost of legalization. Currently we can only lower intrinsics with 1468 // evl but no mask, on Power 9/10. Otherwise, we must scalarize. 1469 return getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind); 1470 } 1471