1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Top-level implementation for the PowerPC target. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCTargetMachine.h" 14 #include "MCTargetDesc/PPCMCTargetDesc.h" 15 #include "PPC.h" 16 #include "PPCMachineScheduler.h" 17 #include "PPCSubtarget.h" 18 #include "PPCTargetObjectFile.h" 19 #include "PPCTargetTransformInfo.h" 20 #include "TargetInfo/PowerPCTargetInfo.h" 21 #include "llvm/ADT/Optional.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/ADT/StringRef.h" 24 #include "llvm/ADT/Triple.h" 25 #include "llvm/Analysis/TargetTransformInfo.h" 26 #include "llvm/CodeGen/Passes.h" 27 #include "llvm/CodeGen/TargetPassConfig.h" 28 #include "llvm/CodeGen/MachineScheduler.h" 29 #include "llvm/IR/Attributes.h" 30 #include "llvm/IR/DataLayout.h" 31 #include "llvm/IR/Function.h" 32 #include "llvm/Pass.h" 33 #include "llvm/Support/CodeGen.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/TargetRegistry.h" 36 #include "llvm/Target/TargetLoweringObjectFile.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include "llvm/Transforms/Scalar.h" 39 #include <cassert> 40 #include <memory> 41 #include <string> 42 43 using namespace llvm; 44 45 46 static cl::opt<bool> 47 EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden, 48 cl::desc("enable coalescing of duplicate branches for PPC")); 49 static cl:: 50 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, 51 cl::desc("Disable CTR loops for PPC")); 52 53 static cl:: 54 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden, 55 cl::desc("Disable PPC loop preinc prep")); 56 57 static cl::opt<bool> 58 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", 59 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early")); 60 61 static cl:: 62 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, 63 cl::desc("Disable VSX Swap Removal for PPC")); 64 65 static cl:: 66 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden, 67 cl::desc("Disable QPX load splat simplification")); 68 69 static cl:: 70 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden, 71 cl::desc("Disable machine peepholes for PPC")); 72 73 static cl::opt<bool> 74 EnableGEPOpt("ppc-gep-opt", cl::Hidden, 75 cl::desc("Enable optimizations on complex GEPs"), 76 cl::init(true)); 77 78 static cl::opt<bool> 79 EnablePrefetch("enable-ppc-prefetching", 80 cl::desc("disable software prefetching on PPC"), 81 cl::init(false), cl::Hidden); 82 83 static cl::opt<bool> 84 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", 85 cl::desc("Add extra TOC register dependencies"), 86 cl::init(true), cl::Hidden); 87 88 static cl::opt<bool> 89 EnableMachineCombinerPass("ppc-machine-combiner", 90 cl::desc("Enable the machine combiner pass"), 91 cl::init(true), cl::Hidden); 92 93 static cl::opt<bool> 94 ReduceCRLogical("ppc-reduce-cr-logicals", 95 cl::desc("Expand eligible cr-logical binary ops to branches"), 96 cl::init(true), cl::Hidden); 97 extern "C" void LLVMInitializePowerPCTarget() { 98 // Register the targets 99 RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target()); 100 RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target()); 101 RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget()); 102 103 PassRegistry &PR = *PassRegistry::getPassRegistry(); 104 #ifndef NDEBUG 105 initializePPCCTRLoopsVerifyPass(PR); 106 #endif 107 initializePPCLoopPreIncPrepPass(PR); 108 initializePPCTOCRegDepsPass(PR); 109 initializePPCEarlyReturnPass(PR); 110 initializePPCVSXCopyPass(PR); 111 initializePPCVSXFMAMutatePass(PR); 112 initializePPCVSXSwapRemovalPass(PR); 113 initializePPCReduceCRLogicalsPass(PR); 114 initializePPCBSelPass(PR); 115 initializePPCBranchCoalescingPass(PR); 116 initializePPCQPXLoadSplatPass(PR); 117 initializePPCBoolRetToIntPass(PR); 118 initializePPCExpandISELPass(PR); 119 initializePPCPreEmitPeepholePass(PR); 120 initializePPCTLSDynamicCallPass(PR); 121 initializePPCMIPeepholePass(PR); 122 } 123 124 /// Return the datalayout string of a subtarget. 125 static std::string getDataLayoutString(const Triple &T) { 126 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le; 127 std::string Ret; 128 129 // Most PPC* platforms are big endian, PPC64LE is little endian. 130 if (T.getArch() == Triple::ppc64le) 131 Ret = "e"; 132 else 133 Ret = "E"; 134 135 Ret += DataLayout::getManglingComponent(T); 136 137 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit 138 // pointers. 139 if (!is64Bit || T.getOS() == Triple::Lv2) 140 Ret += "-p:32:32"; 141 142 // Note, the alignment values for f64 and i64 on ppc64 in Darwin 143 // documentation are wrong; these are correct (i.e. "what gcc does"). 144 if (is64Bit || !T.isOSDarwin()) 145 Ret += "-i64:64"; 146 else 147 Ret += "-f64:32:64"; 148 149 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones. 150 if (is64Bit) 151 Ret += "-n32:64"; 152 else 153 Ret += "-n32"; 154 155 return Ret; 156 } 157 158 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, 159 const Triple &TT) { 160 std::string FullFS = FS; 161 162 // Make sure 64-bit features are available when CPUname is generic 163 if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) { 164 if (!FullFS.empty()) 165 FullFS = "+64bit," + FullFS; 166 else 167 FullFS = "+64bit"; 168 } 169 170 if (OL >= CodeGenOpt::Default) { 171 if (!FullFS.empty()) 172 FullFS = "+crbits," + FullFS; 173 else 174 FullFS = "+crbits"; 175 } 176 177 if (OL != CodeGenOpt::None) { 178 if (!FullFS.empty()) 179 FullFS = "+invariant-function-descriptors," + FullFS; 180 else 181 FullFS = "+invariant-function-descriptors"; 182 } 183 184 return FullFS; 185 } 186 187 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { 188 if (TT.isOSDarwin()) 189 return std::make_unique<TargetLoweringObjectFileMachO>(); 190 191 if (TT.isOSAIX()) 192 return std::make_unique<TargetLoweringObjectFileXCOFF>(); 193 194 return std::make_unique<PPC64LinuxTargetObjectFile>(); 195 } 196 197 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, 198 const TargetOptions &Options) { 199 if (TT.isOSDarwin()) 200 report_fatal_error("Darwin is no longer supported for PowerPC"); 201 202 if (Options.MCOptions.getABIName().startswith("elfv1")) 203 return PPCTargetMachine::PPC_ABI_ELFv1; 204 else if (Options.MCOptions.getABIName().startswith("elfv2")) 205 return PPCTargetMachine::PPC_ABI_ELFv2; 206 207 assert(Options.MCOptions.getABIName().empty() && 208 "Unknown target-abi option!"); 209 210 if (TT.isMacOSX()) 211 return PPCTargetMachine::PPC_ABI_UNKNOWN; 212 213 if (TT.isOSFreeBSD()) { 214 switch (TT.getArch()) { 215 case Triple::ppc64le: 216 case Triple::ppc64: 217 if (TT.getOSMajorVersion() >= 13) 218 return PPCTargetMachine::PPC_ABI_ELFv2; 219 else 220 return PPCTargetMachine::PPC_ABI_ELFv1; 221 case Triple::ppc: 222 default: 223 return PPCTargetMachine::PPC_ABI_UNKNOWN; 224 } 225 } 226 227 switch (TT.getArch()) { 228 case Triple::ppc64le: 229 return PPCTargetMachine::PPC_ABI_ELFv2; 230 case Triple::ppc64: 231 if (TT.getEnvironment() == llvm::Triple::ELFv2) 232 return PPCTargetMachine::PPC_ABI_ELFv2; 233 return PPCTargetMachine::PPC_ABI_ELFv1; 234 default: 235 return PPCTargetMachine::PPC_ABI_UNKNOWN; 236 } 237 } 238 239 static Reloc::Model getEffectiveRelocModel(const Triple &TT, 240 Optional<Reloc::Model> RM) { 241 if (RM.hasValue()) 242 return *RM; 243 244 // Darwin defaults to dynamic-no-pic. 245 if (TT.isOSDarwin()) 246 return Reloc::DynamicNoPIC; 247 248 // Big Endian PPC is PIC by default. 249 if (TT.getArch() == Triple::ppc64) 250 return Reloc::PIC_; 251 252 // Rest are static by default. 253 return Reloc::Static; 254 } 255 256 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT, 257 Optional<CodeModel::Model> CM, 258 bool JIT) { 259 if (CM) { 260 if (*CM == CodeModel::Tiny) 261 report_fatal_error("Target does not support the tiny CodeModel", false); 262 if (*CM == CodeModel::Kernel) 263 report_fatal_error("Target does not support the kernel CodeModel", false); 264 return *CM; 265 } 266 267 if (JIT) 268 return CodeModel::Small; 269 if (TT.isOSAIX()) 270 return CodeModel::Small; 271 272 assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based."); 273 274 if (TT.isArch32Bit()) 275 return CodeModel::Small; 276 277 assert(TT.isArch64Bit() && "Unsupported PPC architecture."); 278 return CodeModel::Medium; 279 } 280 281 282 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) { 283 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>(); 284 ScheduleDAGMILive *DAG = 285 new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ? 286 std::make_unique<PPCPreRASchedStrategy>(C) : 287 std::make_unique<GenericScheduler>(C)); 288 // add DAG Mutations here. 289 DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI)); 290 return DAG; 291 } 292 293 static ScheduleDAGInstrs *createPPCPostMachineScheduler( 294 MachineSchedContext *C) { 295 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>(); 296 ScheduleDAGMI *DAG = 297 new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ? 298 std::make_unique<PPCPostRASchedStrategy>(C) : 299 std::make_unique<PostGenericScheduler>(C), true); 300 // add DAG Mutations here. 301 return DAG; 302 } 303 304 // The FeatureString here is a little subtle. We are modifying the feature 305 // string with what are (currently) non-function specific overrides as it goes 306 // into the LLVMTargetMachine constructor and then using the stored value in the 307 // Subtarget constructor below it. 308 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT, 309 StringRef CPU, StringRef FS, 310 const TargetOptions &Options, 311 Optional<Reloc::Model> RM, 312 Optional<CodeModel::Model> CM, 313 CodeGenOpt::Level OL, bool JIT) 314 : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU, 315 computeFSAdditions(FS, OL, TT), Options, 316 getEffectiveRelocModel(TT, RM), 317 getEffectivePPCCodeModel(TT, CM, JIT), OL), 318 TLOF(createTLOF(getTargetTriple())), 319 TargetABI(computeTargetABI(TT, Options)) { 320 initAsmInfo(); 321 } 322 323 PPCTargetMachine::~PPCTargetMachine() = default; 324 325 const PPCSubtarget * 326 PPCTargetMachine::getSubtargetImpl(const Function &F) const { 327 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 328 Attribute FSAttr = F.getFnAttribute("target-features"); 329 330 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 331 ? CPUAttr.getValueAsString().str() 332 : TargetCPU; 333 std::string FS = !FSAttr.hasAttribute(Attribute::None) 334 ? FSAttr.getValueAsString().str() 335 : TargetFS; 336 337 // FIXME: This is related to the code below to reset the target options, 338 // we need to know whether or not the soft float flag is set on the 339 // function before we can generate a subtarget. We also need to use 340 // it as a key for the subtarget since that can be the only difference 341 // between two functions. 342 bool SoftFloat = 343 F.getFnAttribute("use-soft-float").getValueAsString() == "true"; 344 // If the soft float attribute is set on the function turn on the soft float 345 // subtarget feature. 346 if (SoftFloat) 347 FS += FS.empty() ? "-hard-float" : ",-hard-float"; 348 349 auto &I = SubtargetMap[CPU + FS]; 350 if (!I) { 351 // This needs to be done before we create a new subtarget since any 352 // creation will depend on the TM and the code generation flags on the 353 // function that reside in TargetOptions. 354 resetTargetOptions(F); 355 I = std::make_unique<PPCSubtarget>( 356 TargetTriple, CPU, 357 // FIXME: It would be good to have the subtarget additions here 358 // not necessary. Anything that turns them on/off (overrides) ends 359 // up being put at the end of the feature string, but the defaults 360 // shouldn't require adding them. Fixing this means pulling Feature64Bit 361 // out of most of the target cpus in the .td file and making it set only 362 // as part of initialization via the TargetTriple. 363 computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this); 364 } 365 return I.get(); 366 } 367 368 //===----------------------------------------------------------------------===// 369 // Pass Pipeline Configuration 370 //===----------------------------------------------------------------------===// 371 372 namespace { 373 374 /// PPC Code Generator Pass Configuration Options. 375 class PPCPassConfig : public TargetPassConfig { 376 public: 377 PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM) 378 : TargetPassConfig(TM, PM) { 379 // At any optimization level above -O0 we use the Machine Scheduler and not 380 // the default Post RA List Scheduler. 381 if (TM.getOptLevel() != CodeGenOpt::None) 382 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); 383 } 384 385 PPCTargetMachine &getPPCTargetMachine() const { 386 return getTM<PPCTargetMachine>(); 387 } 388 389 void addIRPasses() override; 390 bool addPreISel() override; 391 bool addILPOpts() override; 392 bool addInstSelector() override; 393 void addMachineSSAOptimization() override; 394 void addPreRegAlloc() override; 395 void addPreSched2() override; 396 void addPreEmitPass() override; 397 ScheduleDAGInstrs * 398 createMachineScheduler(MachineSchedContext *C) const override { 399 return createPPCMachineScheduler(C); 400 } 401 ScheduleDAGInstrs * 402 createPostMachineScheduler(MachineSchedContext *C) const override { 403 return createPPCPostMachineScheduler(C); 404 } 405 }; 406 407 } // end anonymous namespace 408 409 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) { 410 return new PPCPassConfig(*this, PM); 411 } 412 413 void PPCPassConfig::addIRPasses() { 414 if (TM->getOptLevel() != CodeGenOpt::None) 415 addPass(createPPCBoolRetToIntPass()); 416 addPass(createAtomicExpandPass()); 417 418 // For the BG/Q (or if explicitly requested), add explicit data prefetch 419 // intrinsics. 420 bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ && 421 getOptLevel() != CodeGenOpt::None; 422 if (EnablePrefetch.getNumOccurrences() > 0) 423 UsePrefetching = EnablePrefetch; 424 if (UsePrefetching) 425 addPass(createLoopDataPrefetchPass()); 426 427 if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) { 428 // Call SeparateConstOffsetFromGEP pass to extract constants within indices 429 // and lower a GEP with multiple indices to either arithmetic operations or 430 // multiple GEPs with single index. 431 addPass(createSeparateConstOffsetFromGEPPass(true)); 432 // Call EarlyCSE pass to find and remove subexpressions in the lowered 433 // result. 434 addPass(createEarlyCSEPass()); 435 // Do loop invariant code motion in case part of the lowered result is 436 // invariant. 437 addPass(createLICMPass()); 438 } 439 440 TargetPassConfig::addIRPasses(); 441 } 442 443 bool PPCPassConfig::addPreISel() { 444 if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None) 445 addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine())); 446 447 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) 448 addPass(createHardwareLoopsPass()); 449 450 return false; 451 } 452 453 bool PPCPassConfig::addILPOpts() { 454 addPass(&EarlyIfConverterID); 455 456 if (EnableMachineCombinerPass) 457 addPass(&MachineCombinerID); 458 459 return true; 460 } 461 462 bool PPCPassConfig::addInstSelector() { 463 // Install an instruction selector. 464 addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel())); 465 466 #ifndef NDEBUG 467 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) 468 addPass(createPPCCTRLoopsVerify()); 469 #endif 470 471 addPass(createPPCVSXCopyPass()); 472 return false; 473 } 474 475 void PPCPassConfig::addMachineSSAOptimization() { 476 // PPCBranchCoalescingPass need to be done before machine sinking 477 // since it merges empty blocks. 478 if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None) 479 addPass(createPPCBranchCoalescingPass()); 480 TargetPassConfig::addMachineSSAOptimization(); 481 // For little endian, remove where possible the vector swap instructions 482 // introduced at code generation to normalize vector element order. 483 if (TM->getTargetTriple().getArch() == Triple::ppc64le && 484 !DisableVSXSwapRemoval) 485 addPass(createPPCVSXSwapRemovalPass()); 486 // Reduce the number of cr-logical ops. 487 if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None) 488 addPass(createPPCReduceCRLogicalsPass()); 489 // Target-specific peephole cleanups performed after instruction 490 // selection. 491 if (!DisableMIPeephole) { 492 addPass(createPPCMIPeepholePass()); 493 addPass(&DeadMachineInstructionElimID); 494 } 495 } 496 497 void PPCPassConfig::addPreRegAlloc() { 498 if (getOptLevel() != CodeGenOpt::None) { 499 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry()); 500 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID, 501 &PPCVSXFMAMutateID); 502 } 503 504 // FIXME: We probably don't need to run these for -fPIE. 505 if (getPPCTargetMachine().isPositionIndependent()) { 506 // FIXME: LiveVariables should not be necessary here! 507 // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on 508 // LiveVariables. This (unnecessary) dependency has been removed now, 509 // however a stage-2 clang build fails without LiveVariables computed here. 510 addPass(&LiveVariablesID, false); 511 addPass(createPPCTLSDynamicCallPass()); 512 } 513 if (EnableExtraTOCRegDeps) 514 addPass(createPPCTOCRegDepsPass()); 515 516 if (getOptLevel() != CodeGenOpt::None) 517 addPass(&MachinePipelinerID); 518 } 519 520 void PPCPassConfig::addPreSched2() { 521 if (getOptLevel() != CodeGenOpt::None) { 522 addPass(&IfConverterID); 523 524 // This optimization must happen after anything that might do store-to-load 525 // forwarding. Here we're after RA (and, thus, when spills are inserted) 526 // but before post-RA scheduling. 527 if (!DisableQPXLoadSplat) 528 addPass(createPPCQPXLoadSplatPass()); 529 } 530 } 531 532 void PPCPassConfig::addPreEmitPass() { 533 addPass(createPPCPreEmitPeepholePass()); 534 addPass(createPPCExpandISELPass()); 535 536 if (getOptLevel() != CodeGenOpt::None) 537 addPass(createPPCEarlyReturnPass(), false); 538 // Must run branch selection immediately preceding the asm printer. 539 addPass(createPPCBranchSelectionPass(), false); 540 } 541 542 TargetTransformInfo 543 PPCTargetMachine::getTargetTransformInfo(const Function &F) { 544 return TargetTransformInfo(PPCTTIImpl(this, F)); 545 } 546 547 static MachineSchedRegistry 548 PPCPreRASchedRegistry("ppc-prera", 549 "Run PowerPC PreRA specific scheduler", 550 createPPCMachineScheduler); 551 552 static MachineSchedRegistry 553 PPCPostRASchedRegistry("ppc-postra", 554 "Run PowerPC PostRA specific scheduler", 555 createPPCPostMachineScheduler); 556