xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp (revision 6966ac055c3b7a39266fb982493330df7a097997)
1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "TargetInfo/PowerPCTargetInfo.h"
21 #include "llvm/ADT/Optional.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Triple.h"
25 #include "llvm/Analysis/TargetTransformInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/TargetPassConfig.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/IR/Attributes.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/Pass.h"
33 #include "llvm/Support/CodeGen.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/TargetRegistry.h"
36 #include "llvm/Target/TargetLoweringObjectFile.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Transforms/Scalar.h"
39 #include <cassert>
40 #include <memory>
41 #include <string>
42 
43 using namespace llvm;
44 
45 
46 static cl::opt<bool>
47     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
48                            cl::desc("enable coalescing of duplicate branches for PPC"));
49 static cl::
50 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
51                         cl::desc("Disable CTR loops for PPC"));
52 
53 static cl::
54 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
55                             cl::desc("Disable PPC loop preinc prep"));
56 
57 static cl::opt<bool>
58 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
59   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
60 
61 static cl::
62 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
63                                 cl::desc("Disable VSX Swap Removal for PPC"));
64 
65 static cl::
66 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
67                               cl::desc("Disable QPX load splat simplification"));
68 
69 static cl::
70 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
71                             cl::desc("Disable machine peepholes for PPC"));
72 
73 static cl::opt<bool>
74 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
75              cl::desc("Enable optimizations on complex GEPs"),
76              cl::init(true));
77 
78 static cl::opt<bool>
79 EnablePrefetch("enable-ppc-prefetching",
80                   cl::desc("disable software prefetching on PPC"),
81                   cl::init(false), cl::Hidden);
82 
83 static cl::opt<bool>
84 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
85                       cl::desc("Add extra TOC register dependencies"),
86                       cl::init(true), cl::Hidden);
87 
88 static cl::opt<bool>
89 EnableMachineCombinerPass("ppc-machine-combiner",
90                           cl::desc("Enable the machine combiner pass"),
91                           cl::init(true), cl::Hidden);
92 
93 static cl::opt<bool>
94   ReduceCRLogical("ppc-reduce-cr-logicals",
95                   cl::desc("Expand eligible cr-logical binary ops to branches"),
96                   cl::init(false), cl::Hidden);
97 extern "C" void LLVMInitializePowerPCTarget() {
98   // Register the targets
99   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
100   RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
101   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
102 
103   PassRegistry &PR = *PassRegistry::getPassRegistry();
104 #ifndef NDEBUG
105   initializePPCCTRLoopsVerifyPass(PR);
106 #endif
107   initializePPCLoopPreIncPrepPass(PR);
108   initializePPCTOCRegDepsPass(PR);
109   initializePPCEarlyReturnPass(PR);
110   initializePPCVSXCopyPass(PR);
111   initializePPCVSXFMAMutatePass(PR);
112   initializePPCVSXSwapRemovalPass(PR);
113   initializePPCReduceCRLogicalsPass(PR);
114   initializePPCBSelPass(PR);
115   initializePPCBranchCoalescingPass(PR);
116   initializePPCQPXLoadSplatPass(PR);
117   initializePPCBoolRetToIntPass(PR);
118   initializePPCExpandISELPass(PR);
119   initializePPCPreEmitPeepholePass(PR);
120   initializePPCTLSDynamicCallPass(PR);
121   initializePPCMIPeepholePass(PR);
122 }
123 
124 /// Return the datalayout string of a subtarget.
125 static std::string getDataLayoutString(const Triple &T) {
126   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
127   std::string Ret;
128 
129   // Most PPC* platforms are big endian, PPC64LE is little endian.
130   if (T.getArch() == Triple::ppc64le)
131     Ret = "e";
132   else
133     Ret = "E";
134 
135   Ret += DataLayout::getManglingComponent(T);
136 
137   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
138   // pointers.
139   if (!is64Bit || T.getOS() == Triple::Lv2)
140     Ret += "-p:32:32";
141 
142   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
143   // documentation are wrong; these are correct (i.e. "what gcc does").
144   if (is64Bit || !T.isOSDarwin())
145     Ret += "-i64:64";
146   else
147     Ret += "-f64:32:64";
148 
149   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
150   if (is64Bit)
151     Ret += "-n32:64";
152   else
153     Ret += "-n32";
154 
155   return Ret;
156 }
157 
158 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
159                                       const Triple &TT) {
160   std::string FullFS = FS;
161 
162   // Make sure 64-bit features are available when CPUname is generic
163   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
164     if (!FullFS.empty())
165       FullFS = "+64bit," + FullFS;
166     else
167       FullFS = "+64bit";
168   }
169 
170   if (OL >= CodeGenOpt::Default) {
171     if (!FullFS.empty())
172       FullFS = "+crbits," + FullFS;
173     else
174       FullFS = "+crbits";
175   }
176 
177   if (OL != CodeGenOpt::None) {
178     if (!FullFS.empty())
179       FullFS = "+invariant-function-descriptors," + FullFS;
180     else
181       FullFS = "+invariant-function-descriptors";
182   }
183 
184   return FullFS;
185 }
186 
187 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
188   // If it isn't a Mach-O file then it's going to be a linux ELF
189   // object file.
190   if (TT.isOSDarwin())
191     return llvm::make_unique<TargetLoweringObjectFileMachO>();
192 
193   return llvm::make_unique<PPC64LinuxTargetObjectFile>();
194 }
195 
196 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
197                                                  const TargetOptions &Options) {
198   if (TT.isOSDarwin())
199     report_fatal_error("Darwin is no longer supported for PowerPC");
200 
201   if (Options.MCOptions.getABIName().startswith("elfv1"))
202     return PPCTargetMachine::PPC_ABI_ELFv1;
203   else if (Options.MCOptions.getABIName().startswith("elfv2"))
204     return PPCTargetMachine::PPC_ABI_ELFv2;
205 
206   assert(Options.MCOptions.getABIName().empty() &&
207          "Unknown target-abi option!");
208 
209   if (TT.isMacOSX())
210     return PPCTargetMachine::PPC_ABI_UNKNOWN;
211 
212   if (TT.isOSFreeBSD()) {
213     switch (TT.getArch()) {
214     case Triple::ppc64le:
215     case Triple::ppc64:
216       if (TT.getOSMajorVersion() >= 13)
217         return PPCTargetMachine::PPC_ABI_ELFv2;
218       else
219         return PPCTargetMachine::PPC_ABI_ELFv1;
220     case Triple::ppc:
221     default:
222       return PPCTargetMachine::PPC_ABI_UNKNOWN;
223     }
224   }
225 
226   switch (TT.getArch()) {
227   case Triple::ppc64le:
228     return PPCTargetMachine::PPC_ABI_ELFv2;
229   case Triple::ppc64:
230     if (TT.getEnvironment() == llvm::Triple::ELFv2)
231       return PPCTargetMachine::PPC_ABI_ELFv2;
232     return PPCTargetMachine::PPC_ABI_ELFv1;
233   default:
234     return PPCTargetMachine::PPC_ABI_UNKNOWN;
235   }
236 }
237 
238 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
239                                            Optional<Reloc::Model> RM) {
240   if (RM.hasValue())
241     return *RM;
242 
243   // Darwin defaults to dynamic-no-pic.
244   if (TT.isOSDarwin())
245     return Reloc::DynamicNoPIC;
246 
247   // Big Endian PPC is PIC by default.
248   if (TT.getArch() == Triple::ppc64)
249     return Reloc::PIC_;
250 
251   // Rest are static by default.
252   return Reloc::Static;
253 }
254 
255 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
256                                                  Optional<CodeModel::Model> CM,
257                                                  bool JIT) {
258   if (CM) {
259     if (*CM == CodeModel::Tiny)
260       report_fatal_error("Target does not support the tiny CodeModel", false);
261     if (*CM == CodeModel::Kernel)
262       report_fatal_error("Target does not support the kernel CodeModel", false);
263     return *CM;
264   }
265   if (!TT.isOSDarwin() && !JIT &&
266       (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
267     return CodeModel::Medium;
268   return CodeModel::Small;
269 }
270 
271 
272 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
273   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
274   ScheduleDAGMILive *DAG =
275     new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
276                           llvm::make_unique<PPCPreRASchedStrategy>(C) :
277                           llvm::make_unique<GenericScheduler>(C));
278   // add DAG Mutations here.
279   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
280   return DAG;
281 }
282 
283 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
284   MachineSchedContext *C) {
285   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
286   ScheduleDAGMI *DAG =
287     new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
288                       llvm::make_unique<PPCPostRASchedStrategy>(C) :
289                       llvm::make_unique<PostGenericScheduler>(C), true);
290   // add DAG Mutations here.
291   return DAG;
292 }
293 
294 // The FeatureString here is a little subtle. We are modifying the feature
295 // string with what are (currently) non-function specific overrides as it goes
296 // into the LLVMTargetMachine constructor and then using the stored value in the
297 // Subtarget constructor below it.
298 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
299                                    StringRef CPU, StringRef FS,
300                                    const TargetOptions &Options,
301                                    Optional<Reloc::Model> RM,
302                                    Optional<CodeModel::Model> CM,
303                                    CodeGenOpt::Level OL, bool JIT)
304     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
305                         computeFSAdditions(FS, OL, TT), Options,
306                         getEffectiveRelocModel(TT, RM),
307                         getEffectivePPCCodeModel(TT, CM, JIT), OL),
308       TLOF(createTLOF(getTargetTriple())),
309       TargetABI(computeTargetABI(TT, Options)) {
310   initAsmInfo();
311 }
312 
313 PPCTargetMachine::~PPCTargetMachine() = default;
314 
315 const PPCSubtarget *
316 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
317   Attribute CPUAttr = F.getFnAttribute("target-cpu");
318   Attribute FSAttr = F.getFnAttribute("target-features");
319 
320   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
321                         ? CPUAttr.getValueAsString().str()
322                         : TargetCPU;
323   std::string FS = !FSAttr.hasAttribute(Attribute::None)
324                        ? FSAttr.getValueAsString().str()
325                        : TargetFS;
326 
327   // FIXME: This is related to the code below to reset the target options,
328   // we need to know whether or not the soft float flag is set on the
329   // function before we can generate a subtarget. We also need to use
330   // it as a key for the subtarget since that can be the only difference
331   // between two functions.
332   bool SoftFloat =
333       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
334   // If the soft float attribute is set on the function turn on the soft float
335   // subtarget feature.
336   if (SoftFloat)
337     FS += FS.empty() ? "-hard-float" : ",-hard-float";
338 
339   auto &I = SubtargetMap[CPU + FS];
340   if (!I) {
341     // This needs to be done before we create a new subtarget since any
342     // creation will depend on the TM and the code generation flags on the
343     // function that reside in TargetOptions.
344     resetTargetOptions(F);
345     I = llvm::make_unique<PPCSubtarget>(
346         TargetTriple, CPU,
347         // FIXME: It would be good to have the subtarget additions here
348         // not necessary. Anything that turns them on/off (overrides) ends
349         // up being put at the end of the feature string, but the defaults
350         // shouldn't require adding them. Fixing this means pulling Feature64Bit
351         // out of most of the target cpus in the .td file and making it set only
352         // as part of initialization via the TargetTriple.
353         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
354   }
355   return I.get();
356 }
357 
358 //===----------------------------------------------------------------------===//
359 // Pass Pipeline Configuration
360 //===----------------------------------------------------------------------===//
361 
362 namespace {
363 
364 /// PPC Code Generator Pass Configuration Options.
365 class PPCPassConfig : public TargetPassConfig {
366 public:
367   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
368     : TargetPassConfig(TM, PM) {
369     // At any optimization level above -O0 we use the Machine Scheduler and not
370     // the default Post RA List Scheduler.
371     if (TM.getOptLevel() != CodeGenOpt::None)
372       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
373   }
374 
375   PPCTargetMachine &getPPCTargetMachine() const {
376     return getTM<PPCTargetMachine>();
377   }
378 
379   void addIRPasses() override;
380   bool addPreISel() override;
381   bool addILPOpts() override;
382   bool addInstSelector() override;
383   void addMachineSSAOptimization() override;
384   void addPreRegAlloc() override;
385   void addPreSched2() override;
386   void addPreEmitPass() override;
387   ScheduleDAGInstrs *
388   createMachineScheduler(MachineSchedContext *C) const override {
389     return createPPCMachineScheduler(C);
390   }
391   ScheduleDAGInstrs *
392   createPostMachineScheduler(MachineSchedContext *C) const override {
393     return createPPCPostMachineScheduler(C);
394   }
395 };
396 
397 } // end anonymous namespace
398 
399 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
400   return new PPCPassConfig(*this, PM);
401 }
402 
403 void PPCPassConfig::addIRPasses() {
404   if (TM->getOptLevel() != CodeGenOpt::None)
405     addPass(createPPCBoolRetToIntPass());
406   addPass(createAtomicExpandPass());
407 
408   // For the BG/Q (or if explicitly requested), add explicit data prefetch
409   // intrinsics.
410   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
411                         getOptLevel() != CodeGenOpt::None;
412   if (EnablePrefetch.getNumOccurrences() > 0)
413     UsePrefetching = EnablePrefetch;
414   if (UsePrefetching)
415     addPass(createLoopDataPrefetchPass());
416 
417   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
418     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
419     // and lower a GEP with multiple indices to either arithmetic operations or
420     // multiple GEPs with single index.
421     addPass(createSeparateConstOffsetFromGEPPass(true));
422     // Call EarlyCSE pass to find and remove subexpressions in the lowered
423     // result.
424     addPass(createEarlyCSEPass());
425     // Do loop invariant code motion in case part of the lowered result is
426     // invariant.
427     addPass(createLICMPass());
428   }
429 
430   TargetPassConfig::addIRPasses();
431 }
432 
433 bool PPCPassConfig::addPreISel() {
434   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
435     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
436 
437   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
438     addPass(createHardwareLoopsPass());
439 
440   return false;
441 }
442 
443 bool PPCPassConfig::addILPOpts() {
444   addPass(&EarlyIfConverterID);
445 
446   if (EnableMachineCombinerPass)
447     addPass(&MachineCombinerID);
448 
449   return true;
450 }
451 
452 bool PPCPassConfig::addInstSelector() {
453   // Install an instruction selector.
454   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
455 
456 #ifndef NDEBUG
457   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
458     addPass(createPPCCTRLoopsVerify());
459 #endif
460 
461   addPass(createPPCVSXCopyPass());
462   return false;
463 }
464 
465 void PPCPassConfig::addMachineSSAOptimization() {
466   // PPCBranchCoalescingPass need to be done before machine sinking
467   // since it merges empty blocks.
468   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
469     addPass(createPPCBranchCoalescingPass());
470   TargetPassConfig::addMachineSSAOptimization();
471   // For little endian, remove where possible the vector swap instructions
472   // introduced at code generation to normalize vector element order.
473   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
474       !DisableVSXSwapRemoval)
475     addPass(createPPCVSXSwapRemovalPass());
476   // Reduce the number of cr-logical ops.
477   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
478     addPass(createPPCReduceCRLogicalsPass());
479   // Target-specific peephole cleanups performed after instruction
480   // selection.
481   if (!DisableMIPeephole) {
482     addPass(createPPCMIPeepholePass());
483     addPass(&DeadMachineInstructionElimID);
484   }
485 }
486 
487 void PPCPassConfig::addPreRegAlloc() {
488   if (getOptLevel() != CodeGenOpt::None) {
489     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
490     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
491                &PPCVSXFMAMutateID);
492   }
493 
494   // FIXME: We probably don't need to run these for -fPIE.
495   if (getPPCTargetMachine().isPositionIndependent()) {
496     // FIXME: LiveVariables should not be necessary here!
497     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
498     // LiveVariables. This (unnecessary) dependency has been removed now,
499     // however a stage-2 clang build fails without LiveVariables computed here.
500     addPass(&LiveVariablesID, false);
501     addPass(createPPCTLSDynamicCallPass());
502   }
503   if (EnableExtraTOCRegDeps)
504     addPass(createPPCTOCRegDepsPass());
505 
506   if (getOptLevel() != CodeGenOpt::None)
507     addPass(&MachinePipelinerID);
508 }
509 
510 void PPCPassConfig::addPreSched2() {
511   if (getOptLevel() != CodeGenOpt::None) {
512     addPass(&IfConverterID);
513 
514     // This optimization must happen after anything that might do store-to-load
515     // forwarding. Here we're after RA (and, thus, when spills are inserted)
516     // but before post-RA scheduling.
517     if (!DisableQPXLoadSplat)
518       addPass(createPPCQPXLoadSplatPass());
519   }
520 }
521 
522 void PPCPassConfig::addPreEmitPass() {
523   addPass(createPPCPreEmitPeepholePass());
524   addPass(createPPCExpandISELPass());
525 
526   if (getOptLevel() != CodeGenOpt::None)
527     addPass(createPPCEarlyReturnPass(), false);
528   // Must run branch selection immediately preceding the asm printer.
529   addPass(createPPCBranchSelectionPass(), false);
530 }
531 
532 TargetTransformInfo
533 PPCTargetMachine::getTargetTransformInfo(const Function &F) {
534   return TargetTransformInfo(PPCTTIImpl(this, F));
535 }
536 
537 static MachineSchedRegistry
538 PPCPreRASchedRegistry("ppc-prera",
539                       "Run PowerPC PreRA specific scheduler",
540                       createPPCMachineScheduler);
541 
542 static MachineSchedRegistry
543 PPCPostRASchedRegistry("ppc-postra",
544                        "Run PowerPC PostRA specific scheduler",
545                        createPPCPostMachineScheduler);
546