1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Top-level implementation for the PowerPC target. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCTargetMachine.h" 14 #include "MCTargetDesc/PPCMCTargetDesc.h" 15 #include "PPC.h" 16 #include "PPCMachineScheduler.h" 17 #include "PPCMacroFusion.h" 18 #include "PPCSubtarget.h" 19 #include "PPCTargetObjectFile.h" 20 #include "PPCTargetTransformInfo.h" 21 #include "TargetInfo/PowerPCTargetInfo.h" 22 #include "llvm/ADT/Optional.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/ADT/Triple.h" 26 #include "llvm/Analysis/TargetTransformInfo.h" 27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h" 28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 29 #include "llvm/CodeGen/GlobalISel/Legalizer.h" 30 #include "llvm/CodeGen/GlobalISel/Localizer.h" 31 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 32 #include "llvm/CodeGen/MachineScheduler.h" 33 #include "llvm/CodeGen/Passes.h" 34 #include "llvm/CodeGen/TargetPassConfig.h" 35 #include "llvm/IR/Attributes.h" 36 #include "llvm/IR/DataLayout.h" 37 #include "llvm/IR/Function.h" 38 #include "llvm/InitializePasses.h" 39 #include "llvm/Pass.h" 40 #include "llvm/Support/CodeGen.h" 41 #include "llvm/Support/CommandLine.h" 42 #include "llvm/Support/TargetRegistry.h" 43 #include "llvm/Target/TargetLoweringObjectFile.h" 44 #include "llvm/Target/TargetOptions.h" 45 #include "llvm/Transforms/Scalar.h" 46 #include <cassert> 47 #include <memory> 48 #include <string> 49 50 using namespace llvm; 51 52 53 static cl::opt<bool> 54 EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden, 55 cl::desc("enable coalescing of duplicate branches for PPC")); 56 static cl:: 57 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, 58 cl::desc("Disable CTR loops for PPC")); 59 60 static cl:: 61 opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden, 62 cl::desc("Disable PPC loop instr form prep")); 63 64 static cl::opt<bool> 65 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", 66 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early")); 67 68 static cl:: 69 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, 70 cl::desc("Disable VSX Swap Removal for PPC")); 71 72 static cl:: 73 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden, 74 cl::desc("Disable machine peepholes for PPC")); 75 76 static cl::opt<bool> 77 EnableGEPOpt("ppc-gep-opt", cl::Hidden, 78 cl::desc("Enable optimizations on complex GEPs"), 79 cl::init(true)); 80 81 static cl::opt<bool> 82 EnablePrefetch("enable-ppc-prefetching", 83 cl::desc("enable software prefetching on PPC"), 84 cl::init(false), cl::Hidden); 85 86 static cl::opt<bool> 87 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", 88 cl::desc("Add extra TOC register dependencies"), 89 cl::init(true), cl::Hidden); 90 91 static cl::opt<bool> 92 EnableMachineCombinerPass("ppc-machine-combiner", 93 cl::desc("Enable the machine combiner pass"), 94 cl::init(true), cl::Hidden); 95 96 static cl::opt<bool> 97 ReduceCRLogical("ppc-reduce-cr-logicals", 98 cl::desc("Expand eligible cr-logical binary ops to branches"), 99 cl::init(true), cl::Hidden); 100 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() { 101 // Register the targets 102 RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target()); 103 RegisterTargetMachine<PPCTargetMachine> B(getThePPC32LETarget()); 104 RegisterTargetMachine<PPCTargetMachine> C(getThePPC64Target()); 105 RegisterTargetMachine<PPCTargetMachine> D(getThePPC64LETarget()); 106 107 PassRegistry &PR = *PassRegistry::getPassRegistry(); 108 #ifndef NDEBUG 109 initializePPCCTRLoopsVerifyPass(PR); 110 #endif 111 initializePPCLoopInstrFormPrepPass(PR); 112 initializePPCTOCRegDepsPass(PR); 113 initializePPCEarlyReturnPass(PR); 114 initializePPCVSXCopyPass(PR); 115 initializePPCVSXFMAMutatePass(PR); 116 initializePPCVSXSwapRemovalPass(PR); 117 initializePPCReduceCRLogicalsPass(PR); 118 initializePPCBSelPass(PR); 119 initializePPCBranchCoalescingPass(PR); 120 initializePPCBoolRetToIntPass(PR); 121 initializePPCExpandISELPass(PR); 122 initializePPCPreEmitPeepholePass(PR); 123 initializePPCTLSDynamicCallPass(PR); 124 initializePPCMIPeepholePass(PR); 125 initializePPCLowerMASSVEntriesPass(PR); 126 initializeGlobalISel(PR); 127 } 128 129 /// Return the datalayout string of a subtarget. 130 static std::string getDataLayoutString(const Triple &T) { 131 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le; 132 std::string Ret; 133 134 // Most PPC* platforms are big endian, PPC(64)LE is little endian. 135 if (T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle) 136 Ret = "e"; 137 else 138 Ret = "E"; 139 140 Ret += DataLayout::getManglingComponent(T); 141 142 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit 143 // pointers. 144 if (!is64Bit || T.getOS() == Triple::Lv2) 145 Ret += "-p:32:32"; 146 147 // Note, the alignment values for f64 and i64 on ppc64 in Darwin 148 // documentation are wrong; these are correct (i.e. "what gcc does"). 149 Ret += "-i64:64"; 150 151 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones. 152 if (is64Bit) 153 Ret += "-n32:64"; 154 else 155 Ret += "-n32"; 156 157 // Specify the vector alignment explicitly. For v256i1 and v512i1, the 158 // calculated alignment would be 256*alignment(i1) and 512*alignment(i1), 159 // which is 256 and 512 bytes - way over aligned. 160 if ((T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppc64) && 161 (T.isOSAIX() || T.isOSLinux())) 162 Ret += "-v256:256:256-v512:512:512"; 163 164 return Ret; 165 } 166 167 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, 168 const Triple &TT) { 169 std::string FullFS = std::string(FS); 170 171 // Make sure 64-bit features are available when CPUname is generic 172 if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) { 173 if (!FullFS.empty()) 174 FullFS = "+64bit," + FullFS; 175 else 176 FullFS = "+64bit"; 177 } 178 179 if (OL >= CodeGenOpt::Default) { 180 if (!FullFS.empty()) 181 FullFS = "+crbits," + FullFS; 182 else 183 FullFS = "+crbits"; 184 } 185 186 if (OL != CodeGenOpt::None) { 187 if (!FullFS.empty()) 188 FullFS = "+invariant-function-descriptors," + FullFS; 189 else 190 FullFS = "+invariant-function-descriptors"; 191 } 192 193 if (TT.isOSAIX()) { 194 if (!FullFS.empty()) 195 FullFS = "+aix," + FullFS; 196 else 197 FullFS = "+aix"; 198 } 199 200 return FullFS; 201 } 202 203 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { 204 if (TT.isOSAIX()) 205 return std::make_unique<TargetLoweringObjectFileXCOFF>(); 206 207 return std::make_unique<PPC64LinuxTargetObjectFile>(); 208 } 209 210 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, 211 const TargetOptions &Options) { 212 if (Options.MCOptions.getABIName().startswith("elfv1")) 213 return PPCTargetMachine::PPC_ABI_ELFv1; 214 else if (Options.MCOptions.getABIName().startswith("elfv2")) 215 return PPCTargetMachine::PPC_ABI_ELFv2; 216 217 assert(Options.MCOptions.getABIName().empty() && 218 "Unknown target-abi option!"); 219 220 if (TT.isMacOSX()) 221 return PPCTargetMachine::PPC_ABI_UNKNOWN; 222 223 switch (TT.getArch()) { 224 case Triple::ppc64le: 225 return PPCTargetMachine::PPC_ABI_ELFv2; 226 case Triple::ppc64: 227 return PPCTargetMachine::PPC_ABI_ELFv1; 228 default: 229 return PPCTargetMachine::PPC_ABI_UNKNOWN; 230 } 231 } 232 233 static Reloc::Model getEffectiveRelocModel(const Triple &TT, 234 Optional<Reloc::Model> RM) { 235 assert((!TT.isOSAIX() || !RM.hasValue() || *RM == Reloc::PIC_) && 236 "Invalid relocation model for AIX."); 237 238 if (RM.hasValue()) 239 return *RM; 240 241 // Big Endian PPC and AIX default to PIC. 242 if (TT.getArch() == Triple::ppc64 || TT.isOSAIX()) 243 return Reloc::PIC_; 244 245 // Rest are static by default. 246 return Reloc::Static; 247 } 248 249 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT, 250 Optional<CodeModel::Model> CM, 251 bool JIT) { 252 if (CM) { 253 if (*CM == CodeModel::Tiny) 254 report_fatal_error("Target does not support the tiny CodeModel", false); 255 if (*CM == CodeModel::Kernel) 256 report_fatal_error("Target does not support the kernel CodeModel", false); 257 return *CM; 258 } 259 260 if (JIT) 261 return CodeModel::Small; 262 if (TT.isOSAIX()) 263 return CodeModel::Small; 264 265 assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based."); 266 267 if (TT.isArch32Bit()) 268 return CodeModel::Small; 269 270 assert(TT.isArch64Bit() && "Unsupported PPC architecture."); 271 return CodeModel::Medium; 272 } 273 274 275 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) { 276 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>(); 277 ScheduleDAGMILive *DAG = 278 new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ? 279 std::make_unique<PPCPreRASchedStrategy>(C) : 280 std::make_unique<GenericScheduler>(C)); 281 // add DAG Mutations here. 282 DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI)); 283 if (ST.hasStoreFusion()) 284 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); 285 if (ST.hasFusion()) 286 DAG->addMutation(createPowerPCMacroFusionDAGMutation()); 287 288 return DAG; 289 } 290 291 static ScheduleDAGInstrs *createPPCPostMachineScheduler( 292 MachineSchedContext *C) { 293 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>(); 294 ScheduleDAGMI *DAG = 295 new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ? 296 std::make_unique<PPCPostRASchedStrategy>(C) : 297 std::make_unique<PostGenericScheduler>(C), true); 298 // add DAG Mutations here. 299 if (ST.hasStoreFusion()) 300 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); 301 if (ST.hasFusion()) 302 DAG->addMutation(createPowerPCMacroFusionDAGMutation()); 303 return DAG; 304 } 305 306 // The FeatureString here is a little subtle. We are modifying the feature 307 // string with what are (currently) non-function specific overrides as it goes 308 // into the LLVMTargetMachine constructor and then using the stored value in the 309 // Subtarget constructor below it. 310 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT, 311 StringRef CPU, StringRef FS, 312 const TargetOptions &Options, 313 Optional<Reloc::Model> RM, 314 Optional<CodeModel::Model> CM, 315 CodeGenOpt::Level OL, bool JIT) 316 : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU, 317 computeFSAdditions(FS, OL, TT), Options, 318 getEffectiveRelocModel(TT, RM), 319 getEffectivePPCCodeModel(TT, CM, JIT), OL), 320 TLOF(createTLOF(getTargetTriple())), 321 TargetABI(computeTargetABI(TT, Options)) { 322 initAsmInfo(); 323 } 324 325 PPCTargetMachine::~PPCTargetMachine() = default; 326 327 const PPCSubtarget * 328 PPCTargetMachine::getSubtargetImpl(const Function &F) const { 329 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 330 Attribute FSAttr = F.getFnAttribute("target-features"); 331 332 std::string CPU = 333 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 334 std::string FS = 335 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 336 337 // FIXME: This is related to the code below to reset the target options, 338 // we need to know whether or not the soft float flag is set on the 339 // function before we can generate a subtarget. We also need to use 340 // it as a key for the subtarget since that can be the only difference 341 // between two functions. 342 bool SoftFloat = 343 F.getFnAttribute("use-soft-float").getValueAsString() == "true"; 344 // If the soft float attribute is set on the function turn on the soft float 345 // subtarget feature. 346 if (SoftFloat) 347 FS += FS.empty() ? "-hard-float" : ",-hard-float"; 348 349 auto &I = SubtargetMap[CPU + FS]; 350 if (!I) { 351 // This needs to be done before we create a new subtarget since any 352 // creation will depend on the TM and the code generation flags on the 353 // function that reside in TargetOptions. 354 resetTargetOptions(F); 355 I = std::make_unique<PPCSubtarget>( 356 TargetTriple, CPU, 357 // FIXME: It would be good to have the subtarget additions here 358 // not necessary. Anything that turns them on/off (overrides) ends 359 // up being put at the end of the feature string, but the defaults 360 // shouldn't require adding them. Fixing this means pulling Feature64Bit 361 // out of most of the target cpus in the .td file and making it set only 362 // as part of initialization via the TargetTriple. 363 computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this); 364 } 365 return I.get(); 366 } 367 368 //===----------------------------------------------------------------------===// 369 // Pass Pipeline Configuration 370 //===----------------------------------------------------------------------===// 371 372 namespace { 373 374 /// PPC Code Generator Pass Configuration Options. 375 class PPCPassConfig : public TargetPassConfig { 376 public: 377 PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM) 378 : TargetPassConfig(TM, PM) { 379 // At any optimization level above -O0 we use the Machine Scheduler and not 380 // the default Post RA List Scheduler. 381 if (TM.getOptLevel() != CodeGenOpt::None) 382 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); 383 } 384 385 PPCTargetMachine &getPPCTargetMachine() const { 386 return getTM<PPCTargetMachine>(); 387 } 388 389 void addIRPasses() override; 390 bool addPreISel() override; 391 bool addILPOpts() override; 392 bool addInstSelector() override; 393 void addMachineSSAOptimization() override; 394 void addPreRegAlloc() override; 395 void addPreSched2() override; 396 void addPreEmitPass() override; 397 // GlobalISEL 398 bool addIRTranslator() override; 399 bool addLegalizeMachineIR() override; 400 bool addRegBankSelect() override; 401 bool addGlobalInstructionSelect() override; 402 403 ScheduleDAGInstrs * 404 createMachineScheduler(MachineSchedContext *C) const override { 405 return createPPCMachineScheduler(C); 406 } 407 ScheduleDAGInstrs * 408 createPostMachineScheduler(MachineSchedContext *C) const override { 409 return createPPCPostMachineScheduler(C); 410 } 411 }; 412 413 } // end anonymous namespace 414 415 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) { 416 return new PPCPassConfig(*this, PM); 417 } 418 419 void PPCPassConfig::addIRPasses() { 420 if (TM->getOptLevel() != CodeGenOpt::None) 421 addPass(createPPCBoolRetToIntPass()); 422 addPass(createAtomicExpandPass()); 423 424 // Lower generic MASSV routines to PowerPC subtarget-specific entries. 425 addPass(createPPCLowerMASSVEntriesPass()); 426 427 // If explicitly requested, add explicit data prefetch intrinsics. 428 if (EnablePrefetch.getNumOccurrences() > 0) 429 addPass(createLoopDataPrefetchPass()); 430 431 if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) { 432 // Call SeparateConstOffsetFromGEP pass to extract constants within indices 433 // and lower a GEP with multiple indices to either arithmetic operations or 434 // multiple GEPs with single index. 435 addPass(createSeparateConstOffsetFromGEPPass(true)); 436 // Call EarlyCSE pass to find and remove subexpressions in the lowered 437 // result. 438 addPass(createEarlyCSEPass()); 439 // Do loop invariant code motion in case part of the lowered result is 440 // invariant. 441 addPass(createLICMPass()); 442 } 443 444 TargetPassConfig::addIRPasses(); 445 } 446 447 bool PPCPassConfig::addPreISel() { 448 if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None) 449 addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine())); 450 451 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) 452 addPass(createHardwareLoopsPass()); 453 454 return false; 455 } 456 457 bool PPCPassConfig::addILPOpts() { 458 addPass(&EarlyIfConverterID); 459 460 if (EnableMachineCombinerPass) 461 addPass(&MachineCombinerID); 462 463 return true; 464 } 465 466 bool PPCPassConfig::addInstSelector() { 467 // Install an instruction selector. 468 addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel())); 469 470 #ifndef NDEBUG 471 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) 472 addPass(createPPCCTRLoopsVerify()); 473 #endif 474 475 addPass(createPPCVSXCopyPass()); 476 return false; 477 } 478 479 void PPCPassConfig::addMachineSSAOptimization() { 480 // PPCBranchCoalescingPass need to be done before machine sinking 481 // since it merges empty blocks. 482 if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None) 483 addPass(createPPCBranchCoalescingPass()); 484 TargetPassConfig::addMachineSSAOptimization(); 485 // For little endian, remove where possible the vector swap instructions 486 // introduced at code generation to normalize vector element order. 487 if (TM->getTargetTriple().getArch() == Triple::ppc64le && 488 !DisableVSXSwapRemoval) 489 addPass(createPPCVSXSwapRemovalPass()); 490 // Reduce the number of cr-logical ops. 491 if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None) 492 addPass(createPPCReduceCRLogicalsPass()); 493 // Target-specific peephole cleanups performed after instruction 494 // selection. 495 if (!DisableMIPeephole) { 496 addPass(createPPCMIPeepholePass()); 497 addPass(&DeadMachineInstructionElimID); 498 } 499 } 500 501 void PPCPassConfig::addPreRegAlloc() { 502 if (getOptLevel() != CodeGenOpt::None) { 503 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry()); 504 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID, 505 &PPCVSXFMAMutateID); 506 } 507 508 // FIXME: We probably don't need to run these for -fPIE. 509 if (getPPCTargetMachine().isPositionIndependent()) { 510 // FIXME: LiveVariables should not be necessary here! 511 // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on 512 // LiveVariables. This (unnecessary) dependency has been removed now, 513 // however a stage-2 clang build fails without LiveVariables computed here. 514 addPass(&LiveVariablesID); 515 addPass(createPPCTLSDynamicCallPass()); 516 } 517 if (EnableExtraTOCRegDeps) 518 addPass(createPPCTOCRegDepsPass()); 519 520 if (getOptLevel() != CodeGenOpt::None) 521 addPass(&MachinePipelinerID); 522 } 523 524 void PPCPassConfig::addPreSched2() { 525 if (getOptLevel() != CodeGenOpt::None) 526 addPass(&IfConverterID); 527 } 528 529 void PPCPassConfig::addPreEmitPass() { 530 addPass(createPPCPreEmitPeepholePass()); 531 addPass(createPPCExpandISELPass()); 532 533 if (getOptLevel() != CodeGenOpt::None) 534 addPass(createPPCEarlyReturnPass()); 535 // Must run branch selection immediately preceding the asm printer. 536 addPass(createPPCBranchSelectionPass()); 537 } 538 539 TargetTransformInfo 540 PPCTargetMachine::getTargetTransformInfo(const Function &F) { 541 return TargetTransformInfo(PPCTTIImpl(this, F)); 542 } 543 544 static MachineSchedRegistry 545 PPCPreRASchedRegistry("ppc-prera", 546 "Run PowerPC PreRA specific scheduler", 547 createPPCMachineScheduler); 548 549 static MachineSchedRegistry 550 PPCPostRASchedRegistry("ppc-postra", 551 "Run PowerPC PostRA specific scheduler", 552 createPPCPostMachineScheduler); 553 554 // Global ISEL 555 bool PPCPassConfig::addIRTranslator() { 556 addPass(new IRTranslator()); 557 return false; 558 } 559 560 bool PPCPassConfig::addLegalizeMachineIR() { 561 addPass(new Legalizer()); 562 return false; 563 } 564 565 bool PPCPassConfig::addRegBankSelect() { 566 addPass(new RegBankSelect()); 567 return false; 568 } 569 570 bool PPCPassConfig::addGlobalInstructionSelect() { 571 addPass(new InstructionSelect()); 572 return false; 573 } 574