xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCSubtarget.h (revision e4e041744071ffade1a1c5e08714ed1d5db8e6a6) 
1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include <string>
25 
26 #define GET_SUBTARGETINFO_HEADER
27 #include "PPCGenSubtargetInfo.inc"
28 
29 // GCC #defines PPC on Linux but we use it as our namespace name
30 #undef PPC
31 
32 namespace llvm {
33 class StringRef;
34 
35 namespace PPC {
36   // -m directive values.
37   enum {
38     DIR_NONE,
39     DIR_32,
40     DIR_440,
41     DIR_601,
42     DIR_602,
43     DIR_603,
44     DIR_7400,
45     DIR_750,
46     DIR_970,
47     DIR_A2,
48     DIR_E500,
49     DIR_E500mc,
50     DIR_E5500,
51     DIR_PWR3,
52     DIR_PWR4,
53     DIR_PWR5,
54     DIR_PWR5X,
55     DIR_PWR6,
56     DIR_PWR6X,
57     DIR_PWR7,
58     DIR_PWR8,
59     DIR_PWR9,
60     DIR_PWR_FUTURE,
61     DIR_64
62   };
63 }
64 
65 class GlobalValue;
66 class TargetMachine;
67 
68 class PPCSubtarget : public PPCGenSubtargetInfo {
69 public:
70   enum POPCNTDKind {
71     POPCNTD_Unavailable,
72     POPCNTD_Slow,
73     POPCNTD_Fast
74   };
75 
76 protected:
77   /// TargetTriple - What processor and OS we're targeting.
78   Triple TargetTriple;
79 
80   /// stackAlignment - The minimum alignment known to hold of the stack frame on
81   /// entry to the function and which must be maintained by every function.
82   Align StackAlignment;
83 
84   /// Selected instruction itineraries (one entry per itinerary class.)
85   InstrItineraryData InstrItins;
86 
87   /// Which cpu directive was used.
88   unsigned CPUDirective;
89 
90   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
91   bool HasMFOCRF;
92   bool Has64BitSupport;
93   bool Use64BitRegs;
94   bool UseCRBits;
95   bool HasHardFloat;
96   bool IsPPC64;
97   bool HasAltivec;
98   bool HasFPU;
99   bool HasSPE;
100   bool HasQPX;
101   bool HasVSX;
102   bool NeedsTwoConstNR;
103   bool HasP8Vector;
104   bool HasP8Altivec;
105   bool HasP8Crypto;
106   bool HasP9Vector;
107   bool HasP9Altivec;
108   bool HasFCPSGN;
109   bool HasFSQRT;
110   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
111   bool HasRecipPrec;
112   bool HasSTFIWX;
113   bool HasLFIWAX;
114   bool HasFPRND;
115   bool HasFPCVT;
116   bool HasISEL;
117   bool HasBPERMD;
118   bool HasExtDiv;
119   bool HasCMPB;
120   bool HasLDBRX;
121   bool IsBookE;
122   bool HasOnlyMSYNC;
123   bool IsE500;
124   bool IsPPC4xx;
125   bool IsPPC6xx;
126   bool FeatureMFTB;
127   bool DeprecatedDST;
128   bool HasLazyResolverStubs;
129   bool IsLittleEndian;
130   bool HasICBT;
131   bool HasInvariantFunctionDescriptors;
132   bool HasPartwordAtomics;
133   bool HasDirectMove;
134   bool HasHTM;
135   bool HasFloat128;
136   bool IsISA3_0;
137   bool UseLongCalls;
138   bool SecurePlt;
139   bool VectorsUseTwoUnits;
140   bool UsePPCPreRASchedStrategy;
141   bool UsePPCPostRASchedStrategy;
142 
143   POPCNTDKind HasPOPCNTD;
144 
145   /// When targeting QPX running a stock PPC64 Linux kernel where the stack
146   /// alignment has not been changed, we need to keep the 16-byte alignment
147   /// of the stack.
148   bool IsQPXStackUnaligned;
149 
150   const PPCTargetMachine &TM;
151   PPCFrameLowering FrameLowering;
152   PPCInstrInfo InstrInfo;
153   PPCTargetLowering TLInfo;
154   SelectionDAGTargetInfo TSInfo;
155 
156 public:
157   /// This constructor initializes the data members to match that
158   /// of the specified triple.
159   ///
160   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
161                const PPCTargetMachine &TM);
162 
163   /// ParseSubtargetFeatures - Parses features string setting specified
164   /// subtarget options.  Definition of function is auto generated by tblgen.
165   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
166 
167   /// getStackAlignment - Returns the minimum alignment known to hold of the
168   /// stack frame on entry to the function and which must be maintained by every
169   /// function for this subtarget.
170   Align getStackAlignment() const { return StackAlignment; }
171 
172   /// getDarwinDirective - Returns the -m directive specified for the cpu.
173   unsigned getDarwinDirective() const { return CPUDirective; }
174 
175   /// getCPUDirective - Returns the -m directive specified for the cpu.
176   ///
177   unsigned getCPUDirective() const { return CPUDirective; }
178 
179   /// getInstrItins - Return the instruction itineraries based on subtarget
180   /// selection.
181   const InstrItineraryData *getInstrItineraryData() const override {
182     return &InstrItins;
183   }
184 
185   const PPCFrameLowering *getFrameLowering() const override {
186     return &FrameLowering;
187   }
188   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
189   const PPCTargetLowering *getTargetLowering() const override {
190     return &TLInfo;
191   }
192   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
193     return &TSInfo;
194   }
195   const PPCRegisterInfo *getRegisterInfo() const override {
196     return &getInstrInfo()->getRegisterInfo();
197   }
198   const PPCTargetMachine &getTargetMachine() const { return TM; }
199 
200   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
201   /// so that we can use initializer lists for subtarget initialization.
202   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
203 
204 private:
205   void initializeEnvironment();
206   void initSubtargetFeatures(StringRef CPU, StringRef FS);
207 
208 public:
209   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
210   ///
211   bool isPPC64() const;
212 
213   /// has64BitSupport - Return true if the selected CPU supports 64-bit
214   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
215   bool has64BitSupport() const { return Has64BitSupport; }
216   // useSoftFloat - Return true if soft-float option is turned on.
217   bool useSoftFloat() const {
218     if (isAIXABI() && !HasHardFloat)
219       report_fatal_error("soft-float is not yet supported on AIX.");
220     return !HasHardFloat;
221   }
222 
223   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
224   /// registers in 32-bit mode when possible.  This can only true if
225   /// has64BitSupport() returns true.
226   bool use64BitRegs() const { return Use64BitRegs; }
227 
228   /// useCRBits - Return true if we should store and manipulate i1 values in
229   /// the individual condition register bits.
230   bool useCRBits() const { return UseCRBits; }
231 
232   /// hasLazyResolverStub - Return true if accesses to the specified global have
233   /// to go through a dyld lazy resolution stub.  This means that an extra load
234   /// is required to get the address of the global.
235   bool hasLazyResolverStub(const GlobalValue *GV) const;
236 
237   // isLittleEndian - True if generating little-endian code
238   bool isLittleEndian() const { return IsLittleEndian; }
239 
240   // Specific obvious features.
241   bool hasFCPSGN() const { return HasFCPSGN; }
242   bool hasFSQRT() const { return HasFSQRT; }
243   bool hasFRE() const { return HasFRE; }
244   bool hasFRES() const { return HasFRES; }
245   bool hasFRSQRTE() const { return HasFRSQRTE; }
246   bool hasFRSQRTES() const { return HasFRSQRTES; }
247   bool hasRecipPrec() const { return HasRecipPrec; }
248   bool hasSTFIWX() const { return HasSTFIWX; }
249   bool hasLFIWAX() const { return HasLFIWAX; }
250   bool hasFPRND() const { return HasFPRND; }
251   bool hasFPCVT() const { return HasFPCVT; }
252   bool hasAltivec() const { return HasAltivec; }
253   bool hasSPE() const { return HasSPE; }
254   bool hasFPU() const { return HasFPU; }
255   bool hasQPX() const { return HasQPX; }
256   bool hasVSX() const { return HasVSX; }
257   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
258   bool hasP8Vector() const { return HasP8Vector; }
259   bool hasP8Altivec() const { return HasP8Altivec; }
260   bool hasP8Crypto() const { return HasP8Crypto; }
261   bool hasP9Vector() const { return HasP9Vector; }
262   bool hasP9Altivec() const { return HasP9Altivec; }
263   bool hasMFOCRF() const { return HasMFOCRF; }
264   bool hasISEL() const { return HasISEL; }
265   bool hasBPERMD() const { return HasBPERMD; }
266   bool hasExtDiv() const { return HasExtDiv; }
267   bool hasCMPB() const { return HasCMPB; }
268   bool hasLDBRX() const { return HasLDBRX; }
269   bool isBookE() const { return IsBookE; }
270   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
271   bool isPPC4xx() const { return IsPPC4xx; }
272   bool isPPC6xx() const { return IsPPC6xx; }
273   bool isSecurePlt() const {return SecurePlt; }
274   bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
275   bool isE500() const { return IsE500; }
276   bool isFeatureMFTB() const { return FeatureMFTB; }
277   bool isDeprecatedDST() const { return DeprecatedDST; }
278   bool hasICBT() const { return HasICBT; }
279   bool hasInvariantFunctionDescriptors() const {
280     return HasInvariantFunctionDescriptors;
281   }
282   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
283   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
284   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
285   bool hasDirectMove() const { return HasDirectMove; }
286 
287   bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
288   Align getPlatformStackAlignment() const {
289     if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
290       return Align(32);
291 
292     return Align(16);
293   }
294 
295   // DarwinABI has a 224-byte red zone. PPC32 SVR4ABI(Non-DarwinABI) has no
296   // red zone and PPC64 SVR4ABI has a 288-byte red zone.
297   unsigned  getRedZoneSize() const {
298     return isDarwinABI() ? 224 : (isPPC64() ? 288 : 0);
299   }
300 
301   bool hasHTM() const { return HasHTM; }
302   bool hasFloat128() const { return HasFloat128; }
303   bool isISA3_0() const { return IsISA3_0; }
304   bool useLongCalls() const { return UseLongCalls; }
305   bool needsSwapsForVSXMemOps() const {
306     return hasVSX() && isLittleEndian() && !hasP9Vector();
307   }
308 
309   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
310 
311   const Triple &getTargetTriple() const { return TargetTriple; }
312 
313   /// isDarwin - True if this is any darwin platform.
314   bool isDarwin() const { return TargetTriple.isMacOSX(); }
315   /// isBGQ - True if this is a BG/Q platform.
316   bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
317 
318   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
319   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
320   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
321 
322   bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
323   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
324   bool isSVR4ABI() const { return !isDarwinABI() && !isAIXABI(); }
325   bool isELFv2ABI() const;
326 
327   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
328   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
329 
330   /// Originally, this function return hasISEL(). Now we always enable it,
331   /// but may expand the ISEL instruction later.
332   bool enableEarlyIfConversion() const override { return true; }
333 
334   /// Scheduling customization.
335   bool enableMachineScheduler() const override;
336   /// Pipeliner customization.
337   bool enableMachinePipeliner() const override;
338   /// Machine Pipeliner customization
339   bool useDFAforSMS() const override;
340   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
341   bool enablePostRAScheduler() const override;
342   AntiDepBreakMode getAntiDepBreakMode() const override;
343   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
344 
345   void overrideSchedPolicy(MachineSchedPolicy &Policy,
346                            unsigned NumRegionInstrs) const override;
347   bool useAA() const override;
348 
349   bool enableSubRegLiveness() const override;
350 
351   /// True if the GV will be accessed via an indirect symbol.
352   bool isGVIndirectSymbol(const GlobalValue *GV) const;
353 
354   /// True if the ABI is descriptor based.
355   bool usesFunctionDescriptors() const {
356     // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
357     // v1 ABI uses descriptors.
358     return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
359   }
360 
361   unsigned descriptorTOCAnchorOffset() const {
362     assert(usesFunctionDescriptors() &&
363            "Should only be called when the target uses descriptors.");
364     return IsPPC64 ? 8 : 4;
365   }
366 
367   unsigned descriptorEnvironmentPointerOffset() const {
368     assert(usesFunctionDescriptors() &&
369            "Should only be called when the target uses descriptors.");
370     return IsPPC64 ? 16 : 8;
371   }
372 
373   MCRegister getEnvironmentPointerRegister() const {
374     assert(usesFunctionDescriptors() &&
375            "Should only be called when the target uses descriptors.");
376      return IsPPC64 ? PPC::X11 : PPC::R11;
377   }
378 
379   MCRegister getTOCPointerRegister() const {
380     assert((is64BitELFABI() || isAIXABI()) &&
381            "Should only be called when the target is a TOC based ABI.");
382     return IsPPC64 ? PPC::X2 : PPC::R2;
383   }
384 
385   MCRegister getStackPointerRegister() const {
386     return IsPPC64 ? PPC::X1 : PPC::R1;
387   }
388 
389   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
390 };
391 } // End llvm namespace
392 
393 #endif
394