xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCSubtarget.h (revision b4af4f93c682e445bf159f0d1ec90b636296c946) 
1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include <string>
25 
26 #define GET_SUBTARGETINFO_HEADER
27 #include "PPCGenSubtargetInfo.inc"
28 
29 // GCC #defines PPC on Linux but we use it as our namespace name
30 #undef PPC
31 
32 namespace llvm {
33 class StringRef;
34 
35 namespace PPC {
36   // -m directive values.
37   enum {
38     DIR_NONE,
39     DIR_32,
40     DIR_440,
41     DIR_601,
42     DIR_602,
43     DIR_603,
44     DIR_7400,
45     DIR_750,
46     DIR_970,
47     DIR_A2,
48     DIR_E500,
49     DIR_E500mc,
50     DIR_E5500,
51     DIR_PWR3,
52     DIR_PWR4,
53     DIR_PWR5,
54     DIR_PWR5X,
55     DIR_PWR6,
56     DIR_PWR6X,
57     DIR_PWR7,
58     DIR_PWR8,
59     DIR_PWR9,
60     DIR_PWR_FUTURE,
61     DIR_64
62   };
63 }
64 
65 class GlobalValue;
66 class TargetMachine;
67 
68 class PPCSubtarget : public PPCGenSubtargetInfo {
69 public:
70   enum POPCNTDKind {
71     POPCNTD_Unavailable,
72     POPCNTD_Slow,
73     POPCNTD_Fast
74   };
75 
76 protected:
77   /// TargetTriple - What processor and OS we're targeting.
78   Triple TargetTriple;
79 
80   /// stackAlignment - The minimum alignment known to hold of the stack frame on
81   /// entry to the function and which must be maintained by every function.
82   Align StackAlignment;
83 
84   /// Selected instruction itineraries (one entry per itinerary class.)
85   InstrItineraryData InstrItins;
86 
87   /// Which cpu directive was used.
88   unsigned CPUDirective;
89 
90   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
91   bool HasMFOCRF;
92   bool Has64BitSupport;
93   bool Use64BitRegs;
94   bool UseCRBits;
95   bool HasHardFloat;
96   bool IsPPC64;
97   bool HasAltivec;
98   bool HasFPU;
99   bool HasSPE;
100   bool HasQPX;
101   bool HasVSX;
102   bool NeedsTwoConstNR;
103   bool HasP8Vector;
104   bool HasP8Altivec;
105   bool HasP8Crypto;
106   bool HasP9Vector;
107   bool HasP9Altivec;
108   bool HasFCPSGN;
109   bool HasFSQRT;
110   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
111   bool HasRecipPrec;
112   bool HasSTFIWX;
113   bool HasLFIWAX;
114   bool HasFPRND;
115   bool HasFPCVT;
116   bool HasISEL;
117   bool HasBPERMD;
118   bool HasExtDiv;
119   bool HasCMPB;
120   bool HasLDBRX;
121   bool IsBookE;
122   bool HasOnlyMSYNC;
123   bool IsE500;
124   bool IsPPC4xx;
125   bool IsPPC6xx;
126   bool FeatureMFTB;
127   bool AllowsUnalignedFPAccess;
128   bool DeprecatedDST;
129   bool HasLazyResolverStubs;
130   bool IsLittleEndian;
131   bool HasICBT;
132   bool HasInvariantFunctionDescriptors;
133   bool HasPartwordAtomics;
134   bool HasDirectMove;
135   bool HasHTM;
136   bool HasFloat128;
137   bool IsISA3_0;
138   bool UseLongCalls;
139   bool SecurePlt;
140   bool VectorsUseTwoUnits;
141   bool UsePPCPreRASchedStrategy;
142   bool UsePPCPostRASchedStrategy;
143 
144   POPCNTDKind HasPOPCNTD;
145 
146   /// When targeting QPX running a stock PPC64 Linux kernel where the stack
147   /// alignment has not been changed, we need to keep the 16-byte alignment
148   /// of the stack.
149   bool IsQPXStackUnaligned;
150 
151   const PPCTargetMachine &TM;
152   PPCFrameLowering FrameLowering;
153   PPCInstrInfo InstrInfo;
154   PPCTargetLowering TLInfo;
155   SelectionDAGTargetInfo TSInfo;
156 
157 public:
158   /// This constructor initializes the data members to match that
159   /// of the specified triple.
160   ///
161   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
162                const PPCTargetMachine &TM);
163 
164   /// ParseSubtargetFeatures - Parses features string setting specified
165   /// subtarget options.  Definition of function is auto generated by tblgen.
166   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
167 
168   /// getStackAlignment - Returns the minimum alignment known to hold of the
169   /// stack frame on entry to the function and which must be maintained by every
170   /// function for this subtarget.
171   Align getStackAlignment() const { return StackAlignment; }
172 
173   /// getDarwinDirective - Returns the -m directive specified for the cpu.
174   unsigned getDarwinDirective() const { return CPUDirective; }
175 
176   /// getCPUDirective - Returns the -m directive specified for the cpu.
177   ///
178   unsigned getCPUDirective() const { return CPUDirective; }
179 
180   /// getInstrItins - Return the instruction itineraries based on subtarget
181   /// selection.
182   const InstrItineraryData *getInstrItineraryData() const override {
183     return &InstrItins;
184   }
185 
186   const PPCFrameLowering *getFrameLowering() const override {
187     return &FrameLowering;
188   }
189   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
190   const PPCTargetLowering *getTargetLowering() const override {
191     return &TLInfo;
192   }
193   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
194     return &TSInfo;
195   }
196   const PPCRegisterInfo *getRegisterInfo() const override {
197     return &getInstrInfo()->getRegisterInfo();
198   }
199   const PPCTargetMachine &getTargetMachine() const { return TM; }
200 
201   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
202   /// so that we can use initializer lists for subtarget initialization.
203   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
204 
205 private:
206   void initializeEnvironment();
207   void initSubtargetFeatures(StringRef CPU, StringRef FS);
208 
209 public:
210   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
211   ///
212   bool isPPC64() const;
213 
214   /// has64BitSupport - Return true if the selected CPU supports 64-bit
215   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
216   bool has64BitSupport() const { return Has64BitSupport; }
217   // useSoftFloat - Return true if soft-float option is turned on.
218   bool useSoftFloat() const {
219     if (isAIXABI() && !HasHardFloat)
220       report_fatal_error("soft-float is not yet supported on AIX.");
221     return !HasHardFloat;
222   }
223 
224   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
225   /// registers in 32-bit mode when possible.  This can only true if
226   /// has64BitSupport() returns true.
227   bool use64BitRegs() const { return Use64BitRegs; }
228 
229   /// useCRBits - Return true if we should store and manipulate i1 values in
230   /// the individual condition register bits.
231   bool useCRBits() const { return UseCRBits; }
232 
233   /// hasLazyResolverStub - Return true if accesses to the specified global have
234   /// to go through a dyld lazy resolution stub.  This means that an extra load
235   /// is required to get the address of the global.
236   bool hasLazyResolverStub(const GlobalValue *GV) const;
237 
238   // isLittleEndian - True if generating little-endian code
239   bool isLittleEndian() const { return IsLittleEndian; }
240 
241   // Specific obvious features.
242   bool hasFCPSGN() const { return HasFCPSGN; }
243   bool hasFSQRT() const { return HasFSQRT; }
244   bool hasFRE() const { return HasFRE; }
245   bool hasFRES() const { return HasFRES; }
246   bool hasFRSQRTE() const { return HasFRSQRTE; }
247   bool hasFRSQRTES() const { return HasFRSQRTES; }
248   bool hasRecipPrec() const { return HasRecipPrec; }
249   bool hasSTFIWX() const { return HasSTFIWX; }
250   bool hasLFIWAX() const { return HasLFIWAX; }
251   bool hasFPRND() const { return HasFPRND; }
252   bool hasFPCVT() const { return HasFPCVT; }
253   bool hasAltivec() const { return HasAltivec; }
254   bool hasSPE() const { return HasSPE; }
255   bool hasFPU() const { return HasFPU; }
256   bool hasQPX() const { return HasQPX; }
257   bool hasVSX() const { return HasVSX; }
258   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
259   bool hasP8Vector() const { return HasP8Vector; }
260   bool hasP8Altivec() const { return HasP8Altivec; }
261   bool hasP8Crypto() const { return HasP8Crypto; }
262   bool hasP9Vector() const { return HasP9Vector; }
263   bool hasP9Altivec() const { return HasP9Altivec; }
264   bool hasMFOCRF() const { return HasMFOCRF; }
265   bool hasISEL() const { return HasISEL; }
266   bool hasBPERMD() const { return HasBPERMD; }
267   bool hasExtDiv() const { return HasExtDiv; }
268   bool hasCMPB() const { return HasCMPB; }
269   bool hasLDBRX() const { return HasLDBRX; }
270   bool isBookE() const { return IsBookE; }
271   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
272   bool isPPC4xx() const { return IsPPC4xx; }
273   bool isPPC6xx() const { return IsPPC6xx; }
274   bool isSecurePlt() const {return SecurePlt; }
275   bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
276   bool isE500() const { return IsE500; }
277   bool isFeatureMFTB() const { return FeatureMFTB; }
278   bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
279   bool isDeprecatedDST() const { return DeprecatedDST; }
280   bool hasICBT() const { return HasICBT; }
281   bool hasInvariantFunctionDescriptors() const {
282     return HasInvariantFunctionDescriptors;
283   }
284   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
285   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
286   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
287   bool hasDirectMove() const { return HasDirectMove; }
288 
289   bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
290   Align getPlatformStackAlignment() const {
291     if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
292       return Align(32);
293 
294     return Align(16);
295   }
296 
297   // DarwinABI has a 224-byte red zone. PPC32 SVR4ABI(Non-DarwinABI) has no
298   // red zone and PPC64 SVR4ABI has a 288-byte red zone.
299   unsigned  getRedZoneSize() const {
300     return isDarwinABI() ? 224 : (isPPC64() ? 288 : 0);
301   }
302 
303   bool hasHTM() const { return HasHTM; }
304   bool hasFloat128() const { return HasFloat128; }
305   bool isISA3_0() const { return IsISA3_0; }
306   bool useLongCalls() const { return UseLongCalls; }
307   bool needsSwapsForVSXMemOps() const {
308     return hasVSX() && isLittleEndian() && !hasP9Vector();
309   }
310 
311   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
312 
313   const Triple &getTargetTriple() const { return TargetTriple; }
314 
315   /// isDarwin - True if this is any darwin platform.
316   bool isDarwin() const { return TargetTriple.isMacOSX(); }
317   /// isBGQ - True if this is a BG/Q platform.
318   bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
319 
320   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
321   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
322   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
323 
324   bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
325   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
326   bool isSVR4ABI() const { return !isDarwinABI() && !isAIXABI(); }
327   bool isELFv2ABI() const;
328 
329   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
330   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
331 
332   /// Originally, this function return hasISEL(). Now we always enable it,
333   /// but may expand the ISEL instruction later.
334   bool enableEarlyIfConversion() const override { return true; }
335 
336   /// Scheduling customization.
337   bool enableMachineScheduler() const override;
338   /// Pipeliner customization.
339   bool enableMachinePipeliner() const override;
340   /// Machine Pipeliner customization
341   bool useDFAforSMS() const override;
342   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
343   bool enablePostRAScheduler() const override;
344   AntiDepBreakMode getAntiDepBreakMode() const override;
345   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
346 
347   void overrideSchedPolicy(MachineSchedPolicy &Policy,
348                            unsigned NumRegionInstrs) const override;
349   bool useAA() const override;
350 
351   bool enableSubRegLiveness() const override;
352 
353   /// True if the GV will be accessed via an indirect symbol.
354   bool isGVIndirectSymbol(const GlobalValue *GV) const;
355 
356   /// True if the ABI is descriptor based.
357   bool usesFunctionDescriptors() const {
358     // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
359     // v1 ABI uses descriptors.
360     return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
361   }
362 
363   unsigned descriptorTOCAnchorOffset() const {
364     assert(usesFunctionDescriptors() &&
365            "Should only be called when the target uses descriptors.");
366     return IsPPC64 ? 8 : 4;
367   }
368 
369   unsigned descriptorEnvironmentPointerOffset() const {
370     assert(usesFunctionDescriptors() &&
371            "Should only be called when the target uses descriptors.");
372     return IsPPC64 ? 16 : 8;
373   }
374 
375   MCRegister getEnvironmentPointerRegister() const {
376     assert(usesFunctionDescriptors() &&
377            "Should only be called when the target uses descriptors.");
378      return IsPPC64 ? PPC::X11 : PPC::R11;
379   }
380 
381   MCRegister getTOCPointerRegister() const {
382     assert((is64BitELFABI() || isAIXABI()) &&
383            "Should only be called when the target is a TOC based ABI.");
384     return IsPPC64 ? PPC::X2 : PPC::R2;
385   }
386 
387   MCRegister getStackPointerRegister() const {
388     return IsPPC64 ? PPC::X1 : PPC::R1;
389   }
390 
391   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
392 };
393 } // End llvm namespace
394 
395 #endif
396