xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCSubtarget.h (revision 8bcb0991864975618c09697b1aca10683346d9f0) 
1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include <string>
25 
26 #define GET_SUBTARGETINFO_HEADER
27 #include "PPCGenSubtargetInfo.inc"
28 
29 // GCC #defines PPC on Linux but we use it as our namespace name
30 #undef PPC
31 
32 namespace llvm {
33 class StringRef;
34 
35 namespace PPC {
36   // -m directive values.
37   enum {
38     DIR_NONE,
39     DIR_32,
40     DIR_440,
41     DIR_601,
42     DIR_602,
43     DIR_603,
44     DIR_7400,
45     DIR_750,
46     DIR_970,
47     DIR_A2,
48     DIR_E500,
49     DIR_E500mc,
50     DIR_E5500,
51     DIR_PWR3,
52     DIR_PWR4,
53     DIR_PWR5,
54     DIR_PWR5X,
55     DIR_PWR6,
56     DIR_PWR6X,
57     DIR_PWR7,
58     DIR_PWR8,
59     DIR_PWR9,
60     DIR_64
61   };
62 }
63 
64 class GlobalValue;
65 class TargetMachine;
66 
67 class PPCSubtarget : public PPCGenSubtargetInfo {
68 public:
69   enum POPCNTDKind {
70     POPCNTD_Unavailable,
71     POPCNTD_Slow,
72     POPCNTD_Fast
73   };
74 
75 protected:
76   /// TargetTriple - What processor and OS we're targeting.
77   Triple TargetTriple;
78 
79   /// stackAlignment - The minimum alignment known to hold of the stack frame on
80   /// entry to the function and which must be maintained by every function.
81   Align StackAlignment;
82 
83   /// Selected instruction itineraries (one entry per itinerary class.)
84   InstrItineraryData InstrItins;
85 
86   /// Which cpu directive was used.
87   unsigned DarwinDirective;
88 
89   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
90   bool HasMFOCRF;
91   bool Has64BitSupport;
92   bool Use64BitRegs;
93   bool UseCRBits;
94   bool HasHardFloat;
95   bool IsPPC64;
96   bool HasAltivec;
97   bool HasFPU;
98   bool HasSPE;
99   bool HasQPX;
100   bool HasVSX;
101   bool NeedsTwoConstNR;
102   bool HasP8Vector;
103   bool HasP8Altivec;
104   bool HasP8Crypto;
105   bool HasP9Vector;
106   bool HasP9Altivec;
107   bool HasFCPSGN;
108   bool HasFSQRT;
109   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
110   bool HasRecipPrec;
111   bool HasSTFIWX;
112   bool HasLFIWAX;
113   bool HasFPRND;
114   bool HasFPCVT;
115   bool HasISEL;
116   bool HasBPERMD;
117   bool HasExtDiv;
118   bool HasCMPB;
119   bool HasLDBRX;
120   bool IsBookE;
121   bool HasOnlyMSYNC;
122   bool IsE500;
123   bool IsPPC4xx;
124   bool IsPPC6xx;
125   bool FeatureMFTB;
126   bool DeprecatedDST;
127   bool HasLazyResolverStubs;
128   bool IsLittleEndian;
129   bool HasICBT;
130   bool HasInvariantFunctionDescriptors;
131   bool HasPartwordAtomics;
132   bool HasDirectMove;
133   bool HasHTM;
134   bool HasFloat128;
135   bool IsISA3_0;
136   bool UseLongCalls;
137   bool SecurePlt;
138   bool VectorsUseTwoUnits;
139   bool UsePPCPreRASchedStrategy;
140   bool UsePPCPostRASchedStrategy;
141 
142   POPCNTDKind HasPOPCNTD;
143 
144   /// When targeting QPX running a stock PPC64 Linux kernel where the stack
145   /// alignment has not been changed, we need to keep the 16-byte alignment
146   /// of the stack.
147   bool IsQPXStackUnaligned;
148 
149   const PPCTargetMachine &TM;
150   PPCFrameLowering FrameLowering;
151   PPCInstrInfo InstrInfo;
152   PPCTargetLowering TLInfo;
153   SelectionDAGTargetInfo TSInfo;
154 
155 public:
156   /// This constructor initializes the data members to match that
157   /// of the specified triple.
158   ///
159   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
160                const PPCTargetMachine &TM);
161 
162   /// ParseSubtargetFeatures - Parses features string setting specified
163   /// subtarget options.  Definition of function is auto generated by tblgen.
164   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
165 
166   /// getStackAlignment - Returns the minimum alignment known to hold of the
167   /// stack frame on entry to the function and which must be maintained by every
168   /// function for this subtarget.
169   Align getStackAlignment() const { return StackAlignment; }
170 
171   /// getDarwinDirective - Returns the -m directive specified for the cpu.
172   ///
173   unsigned getDarwinDirective() const { return DarwinDirective; }
174 
175   /// getInstrItins - Return the instruction itineraries based on subtarget
176   /// selection.
177   const InstrItineraryData *getInstrItineraryData() const override {
178     return &InstrItins;
179   }
180 
181   const PPCFrameLowering *getFrameLowering() const override {
182     return &FrameLowering;
183   }
184   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
185   const PPCTargetLowering *getTargetLowering() const override {
186     return &TLInfo;
187   }
188   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
189     return &TSInfo;
190   }
191   const PPCRegisterInfo *getRegisterInfo() const override {
192     return &getInstrInfo()->getRegisterInfo();
193   }
194   const PPCTargetMachine &getTargetMachine() const { return TM; }
195 
196   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
197   /// so that we can use initializer lists for subtarget initialization.
198   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
199 
200 private:
201   void initializeEnvironment();
202   void initSubtargetFeatures(StringRef CPU, StringRef FS);
203 
204 public:
205   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
206   ///
207   bool isPPC64() const;
208 
209   /// has64BitSupport - Return true if the selected CPU supports 64-bit
210   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
211   bool has64BitSupport() const { return Has64BitSupport; }
212   // useSoftFloat - Return true if soft-float option is turned on.
213   bool useSoftFloat() const {
214     if (isAIXABI() && !HasHardFloat)
215       report_fatal_error("soft-float is not yet supported on AIX.");
216     return !HasHardFloat;
217   }
218 
219   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
220   /// registers in 32-bit mode when possible.  This can only true if
221   /// has64BitSupport() returns true.
222   bool use64BitRegs() const { return Use64BitRegs; }
223 
224   /// useCRBits - Return true if we should store and manipulate i1 values in
225   /// the individual condition register bits.
226   bool useCRBits() const { return UseCRBits; }
227 
228   /// hasLazyResolverStub - Return true if accesses to the specified global have
229   /// to go through a dyld lazy resolution stub.  This means that an extra load
230   /// is required to get the address of the global.
231   bool hasLazyResolverStub(const GlobalValue *GV) const;
232 
233   // isLittleEndian - True if generating little-endian code
234   bool isLittleEndian() const { return IsLittleEndian; }
235 
236   // Specific obvious features.
237   bool hasFCPSGN() const { return HasFCPSGN; }
238   bool hasFSQRT() const { return HasFSQRT; }
239   bool hasFRE() const { return HasFRE; }
240   bool hasFRES() const { return HasFRES; }
241   bool hasFRSQRTE() const { return HasFRSQRTE; }
242   bool hasFRSQRTES() const { return HasFRSQRTES; }
243   bool hasRecipPrec() const { return HasRecipPrec; }
244   bool hasSTFIWX() const { return HasSTFIWX; }
245   bool hasLFIWAX() const { return HasLFIWAX; }
246   bool hasFPRND() const { return HasFPRND; }
247   bool hasFPCVT() const { return HasFPCVT; }
248   bool hasAltivec() const { return HasAltivec; }
249   bool hasSPE() const { return HasSPE; }
250   bool hasFPU() const { return HasFPU; }
251   bool hasQPX() const { return HasQPX; }
252   bool hasVSX() const { return HasVSX; }
253   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
254   bool hasP8Vector() const { return HasP8Vector; }
255   bool hasP8Altivec() const { return HasP8Altivec; }
256   bool hasP8Crypto() const { return HasP8Crypto; }
257   bool hasP9Vector() const { return HasP9Vector; }
258   bool hasP9Altivec() const { return HasP9Altivec; }
259   bool hasMFOCRF() const { return HasMFOCRF; }
260   bool hasISEL() const { return HasISEL; }
261   bool hasBPERMD() const { return HasBPERMD; }
262   bool hasExtDiv() const { return HasExtDiv; }
263   bool hasCMPB() const { return HasCMPB; }
264   bool hasLDBRX() const { return HasLDBRX; }
265   bool isBookE() const { return IsBookE; }
266   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
267   bool isPPC4xx() const { return IsPPC4xx; }
268   bool isPPC6xx() const { return IsPPC6xx; }
269   bool isSecurePlt() const {return SecurePlt; }
270   bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
271   bool isE500() const { return IsE500; }
272   bool isFeatureMFTB() const { return FeatureMFTB; }
273   bool isDeprecatedDST() const { return DeprecatedDST; }
274   bool hasICBT() const { return HasICBT; }
275   bool hasInvariantFunctionDescriptors() const {
276     return HasInvariantFunctionDescriptors;
277   }
278   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
279   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
280   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
281   bool hasDirectMove() const { return HasDirectMove; }
282 
283   bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
284   Align getPlatformStackAlignment() const {
285     if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
286       return Align(32);
287 
288     return Align(16);
289   }
290 
291   // DarwinABI has a 224-byte red zone. PPC32 SVR4ABI(Non-DarwinABI) has no
292   // red zone and PPC64 SVR4ABI has a 288-byte red zone.
293   unsigned  getRedZoneSize() const {
294     return isDarwinABI() ? 224 : (isPPC64() ? 288 : 0);
295   }
296 
297   bool hasHTM() const { return HasHTM; }
298   bool hasFloat128() const { return HasFloat128; }
299   bool isISA3_0() const { return IsISA3_0; }
300   bool useLongCalls() const { return UseLongCalls; }
301   bool needsSwapsForVSXMemOps() const {
302     return hasVSX() && isLittleEndian() && !hasP9Vector();
303   }
304 
305   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
306 
307   const Triple &getTargetTriple() const { return TargetTriple; }
308 
309   /// isDarwin - True if this is any darwin platform.
310   bool isDarwin() const { return TargetTriple.isMacOSX(); }
311   /// isBGQ - True if this is a BG/Q platform.
312   bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
313 
314   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
315   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
316   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
317 
318   bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
319   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
320   bool isSVR4ABI() const { return !isDarwinABI() && !isAIXABI(); }
321   bool isELFv2ABI() const;
322 
323   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
324   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
325 
326   /// Originally, this function return hasISEL(). Now we always enable it,
327   /// but may expand the ISEL instruction later.
328   bool enableEarlyIfConversion() const override { return true; }
329 
330   /// Scheduling customization.
331   bool enableMachineScheduler() const override;
332   /// Pipeliner customization.
333   bool enableMachinePipeliner() const override;
334   /// Machine Pipeliner customization
335   bool useDFAforSMS() const override;
336   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
337   bool enablePostRAScheduler() const override;
338   AntiDepBreakMode getAntiDepBreakMode() const override;
339   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
340 
341   void overrideSchedPolicy(MachineSchedPolicy &Policy,
342                            unsigned NumRegionInstrs) const override;
343   bool useAA() const override;
344 
345   bool enableSubRegLiveness() const override;
346 
347   /// True if the GV will be accessed via an indirect symbol.
348   bool isGVIndirectSymbol(const GlobalValue *GV) const;
349 
350   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
351 };
352 } // End llvm namespace
353 
354 #endif
355