xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCSubtarget.h (revision 643ac419fafba89f5adda0e0ea75b538727453fb) 
1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
21 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
22 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
23 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/MC/MCInstrItineraries.h"
27 #include <string>
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "PPCGenSubtargetInfo.inc"
31 
32 // GCC #defines PPC on Linux but we use it as our namespace name
33 #undef PPC
34 
35 namespace llvm {
36 class StringRef;
37 
38 namespace PPC {
39   // -m directive values.
40 enum {
41   DIR_NONE,
42   DIR_32,
43   DIR_440,
44   DIR_601,
45   DIR_602,
46   DIR_603,
47   DIR_7400,
48   DIR_750,
49   DIR_970,
50   DIR_A2,
51   DIR_E500,
52   DIR_E500mc,
53   DIR_E5500,
54   DIR_PWR3,
55   DIR_PWR4,
56   DIR_PWR5,
57   DIR_PWR5X,
58   DIR_PWR6,
59   DIR_PWR6X,
60   DIR_PWR7,
61   DIR_PWR8,
62   DIR_PWR9,
63   DIR_PWR10,
64   DIR_PWR_FUTURE,
65   DIR_64
66 };
67 }
68 
69 class GlobalValue;
70 
71 class PPCSubtarget : public PPCGenSubtargetInfo {
72 public:
73   enum POPCNTDKind {
74     POPCNTD_Unavailable,
75     POPCNTD_Slow,
76     POPCNTD_Fast
77   };
78 
79 protected:
80   /// TargetTriple - What processor and OS we're targeting.
81   Triple TargetTriple;
82 
83   /// stackAlignment - The minimum alignment known to hold of the stack frame on
84   /// entry to the function and which must be maintained by every function.
85   Align StackAlignment;
86 
87   /// Selected instruction itineraries (one entry per itinerary class.)
88   InstrItineraryData InstrItins;
89 
90   /// Which cpu directive was used.
91   unsigned CPUDirective;
92 
93   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
94   bool HasMFOCRF;
95   bool Has64BitSupport;
96   bool Use64BitRegs;
97   bool UseCRBits;
98   bool HasHardFloat;
99   bool IsPPC64;
100   bool HasAltivec;
101   bool HasFPU;
102   bool HasSPE;
103   bool HasEFPU2;
104   bool HasVSX;
105   bool NeedsTwoConstNR;
106   bool HasP8Vector;
107   bool HasP8Altivec;
108   bool HasP8Crypto;
109   bool HasP9Vector;
110   bool HasP9Altivec;
111   bool HasP10Vector;
112   bool HasPrefixInstrs;
113   bool HasPCRelativeMemops;
114   bool HasMMA;
115   bool HasROPProtect;
116   bool HasPrivileged;
117   bool HasFCPSGN;
118   bool HasFSQRT;
119   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
120   bool HasRecipPrec;
121   bool HasSTFIWX;
122   bool HasLFIWAX;
123   bool HasFPRND;
124   bool HasFPCVT;
125   bool HasISEL;
126   bool HasBPERMD;
127   bool HasExtDiv;
128   bool HasCMPB;
129   bool HasLDBRX;
130   bool IsBookE;
131   bool HasOnlyMSYNC;
132   bool IsE500;
133   bool IsPPC4xx;
134   bool IsPPC6xx;
135   bool FeatureMFTB;
136   bool AllowsUnalignedFPAccess;
137   bool DeprecatedDST;
138   bool IsLittleEndian;
139   bool HasICBT;
140   bool HasInvariantFunctionDescriptors;
141   bool HasPartwordAtomics;
142   bool HasQuadwordAtomics;
143   bool HasDirectMove;
144   bool HasHTM;
145   bool HasFloat128;
146   bool HasFusion;
147   bool HasStoreFusion;
148   bool HasAddiLoadFusion;
149   bool HasAddisLoadFusion;
150   bool HasArithAddFusion;
151   bool HasAddLogicalFusion;
152   bool HasLogicalAddFusion;
153   bool HasLogicalFusion;
154   bool HasSha3Fusion;
155   bool HasCompareFusion;
156   bool HasWideImmFusion;
157   bool HasZeroMoveFusion;
158   bool HasBack2BackFusion;
159   bool IsISA2_06;
160   bool IsISA2_07;
161   bool IsISA3_0;
162   bool IsISA3_1;
163   bool UseLongCalls;
164   bool SecurePlt;
165   bool VectorsUseTwoUnits;
166   bool UsePPCPreRASchedStrategy;
167   bool UsePPCPostRASchedStrategy;
168   bool PairedVectorMemops;
169   bool PredictableSelectIsExpensive;
170   bool HasModernAIXAs;
171   bool IsAIX;
172 
173   POPCNTDKind HasPOPCNTD;
174 
175   const PPCTargetMachine &TM;
176   PPCFrameLowering FrameLowering;
177   PPCInstrInfo InstrInfo;
178   PPCTargetLowering TLInfo;
179   SelectionDAGTargetInfo TSInfo;
180 
181   /// GlobalISel related APIs.
182   std::unique_ptr<CallLowering> CallLoweringInfo;
183   std::unique_ptr<LegalizerInfo> Legalizer;
184   std::unique_ptr<RegisterBankInfo> RegBankInfo;
185   std::unique_ptr<InstructionSelector> InstSelector;
186 
187 public:
188   /// This constructor initializes the data members to match that
189   /// of the specified triple.
190   ///
191   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
192                const PPCTargetMachine &TM);
193 
194   /// ParseSubtargetFeatures - Parses features string setting specified
195   /// subtarget options.  Definition of function is auto generated by tblgen.
196   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
197 
198   /// getStackAlignment - Returns the minimum alignment known to hold of the
199   /// stack frame on entry to the function and which must be maintained by every
200   /// function for this subtarget.
201   Align getStackAlignment() const { return StackAlignment; }
202 
203   /// getCPUDirective - Returns the -m directive specified for the cpu.
204   ///
205   unsigned getCPUDirective() const { return CPUDirective; }
206 
207   /// getInstrItins - Return the instruction itineraries based on subtarget
208   /// selection.
209   const InstrItineraryData *getInstrItineraryData() const override {
210     return &InstrItins;
211   }
212 
213   const PPCFrameLowering *getFrameLowering() const override {
214     return &FrameLowering;
215   }
216   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
217   const PPCTargetLowering *getTargetLowering() const override {
218     return &TLInfo;
219   }
220   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
221     return &TSInfo;
222   }
223   const PPCRegisterInfo *getRegisterInfo() const override {
224     return &getInstrInfo()->getRegisterInfo();
225   }
226   const PPCTargetMachine &getTargetMachine() const { return TM; }
227 
228   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
229   /// so that we can use initializer lists for subtarget initialization.
230   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
231 
232 private:
233   void initializeEnvironment();
234   void initSubtargetFeatures(StringRef CPU, StringRef FS);
235 
236 public:
237   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
238   ///
239   bool isPPC64() const;
240 
241   /// has64BitSupport - Return true if the selected CPU supports 64-bit
242   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
243   bool has64BitSupport() const { return Has64BitSupport; }
244   // useSoftFloat - Return true if soft-float option is turned on.
245   bool useSoftFloat() const {
246     if (isAIXABI() && !HasHardFloat)
247       report_fatal_error("soft-float is not yet supported on AIX.");
248     return !HasHardFloat;
249   }
250 
251   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
252   /// registers in 32-bit mode when possible.  This can only true if
253   /// has64BitSupport() returns true.
254   bool use64BitRegs() const { return Use64BitRegs; }
255 
256   /// useCRBits - Return true if we should store and manipulate i1 values in
257   /// the individual condition register bits.
258   bool useCRBits() const { return UseCRBits; }
259 
260   // isLittleEndian - True if generating little-endian code
261   bool isLittleEndian() const { return IsLittleEndian; }
262 
263   // Specific obvious features.
264   bool hasFCPSGN() const { return HasFCPSGN; }
265   bool hasFSQRT() const { return HasFSQRT; }
266   bool hasFRE() const { return HasFRE; }
267   bool hasFRES() const { return HasFRES; }
268   bool hasFRSQRTE() const { return HasFRSQRTE; }
269   bool hasFRSQRTES() const { return HasFRSQRTES; }
270   bool hasRecipPrec() const { return HasRecipPrec; }
271   bool hasSTFIWX() const { return HasSTFIWX; }
272   bool hasLFIWAX() const { return HasLFIWAX; }
273   bool hasFPRND() const { return HasFPRND; }
274   bool hasFPCVT() const { return HasFPCVT; }
275   bool hasAltivec() const { return HasAltivec; }
276   bool hasSPE() const { return HasSPE; }
277   bool hasEFPU2() const { return HasEFPU2; }
278   bool hasFPU() const { return HasFPU; }
279   bool hasVSX() const { return HasVSX; }
280   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
281   bool hasP8Vector() const { return HasP8Vector; }
282   bool hasP8Altivec() const { return HasP8Altivec; }
283   bool hasP8Crypto() const { return HasP8Crypto; }
284   bool hasP9Vector() const { return HasP9Vector; }
285   bool hasP9Altivec() const { return HasP9Altivec; }
286   bool hasP10Vector() const { return HasP10Vector; }
287   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
288   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
289   bool hasMMA() const { return HasMMA; }
290   bool hasROPProtect() const { return HasROPProtect; }
291   bool hasPrivileged() const { return HasPrivileged; }
292   bool pairedVectorMemops() const { return PairedVectorMemops; }
293   bool hasMFOCRF() const { return HasMFOCRF; }
294   bool hasISEL() const { return HasISEL; }
295   bool hasBPERMD() const { return HasBPERMD; }
296   bool hasExtDiv() const { return HasExtDiv; }
297   bool hasCMPB() const { return HasCMPB; }
298   bool hasLDBRX() const { return HasLDBRX; }
299   bool isBookE() const { return IsBookE; }
300   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
301   bool isPPC4xx() const { return IsPPC4xx; }
302   bool isPPC6xx() const { return IsPPC6xx; }
303   bool isSecurePlt() const {return SecurePlt; }
304   bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
305   bool isE500() const { return IsE500; }
306   bool isFeatureMFTB() const { return FeatureMFTB; }
307   bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
308   bool isDeprecatedDST() const { return DeprecatedDST; }
309   bool hasICBT() const { return HasICBT; }
310   bool hasInvariantFunctionDescriptors() const {
311     return HasInvariantFunctionDescriptors;
312   }
313   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
314   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
315   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
316   bool hasQuadwordAtomics() const { return HasQuadwordAtomics; }
317   bool hasDirectMove() const { return HasDirectMove; }
318 
319   Align getPlatformStackAlignment() const {
320     return Align(16);
321   }
322 
323   unsigned  getRedZoneSize() const {
324     if (isPPC64())
325       // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
326       return 288;
327 
328     // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
329     // PPC32 SVR4ABI has no redzone.
330     return isAIXABI() ? 220 : 0;
331   }
332 
333   bool hasHTM() const { return HasHTM; }
334   bool hasFloat128() const { return HasFloat128; }
335   bool isISA2_06() const { return IsISA2_06; }
336   bool isISA2_07() const { return IsISA2_07; }
337   bool isISA3_0() const { return IsISA3_0; }
338   bool isISA3_1() const { return IsISA3_1; }
339   bool useLongCalls() const { return UseLongCalls; }
340   bool hasFusion() const { return HasFusion; }
341   bool hasStoreFusion() const { return HasStoreFusion; }
342   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
343   bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
344   bool hasArithAddFusion() const { return HasArithAddFusion; }
345   bool hasAddLogicalFusion() const { return HasAddLogicalFusion; }
346   bool hasLogicalAddFusion() const { return HasLogicalAddFusion; }
347   bool hasLogicalFusion() const { return HasLogicalFusion; }
348   bool hasCompareFusion() const { return HasCompareFusion; }
349   bool hasWideImmFusion() const { return HasWideImmFusion; }
350   bool hasSha3Fusion() const { return HasSha3Fusion; }
351   bool hasZeroMoveFusion() const { return HasZeroMoveFusion; }
352   bool hasBack2BackFusion() const { return HasBack2BackFusion; }
353   bool needsSwapsForVSXMemOps() const {
354     return hasVSX() && isLittleEndian() && !hasP9Vector();
355   }
356 
357   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
358 
359   const Triple &getTargetTriple() const { return TargetTriple; }
360 
361   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
362   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
363   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
364 
365   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
366   bool isSVR4ABI() const { return !isAIXABI(); }
367   bool isELFv2ABI() const;
368 
369   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
370   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
371   bool isUsingPCRelativeCalls() const;
372 
373   /// Originally, this function return hasISEL(). Now we always enable it,
374   /// but may expand the ISEL instruction later.
375   bool enableEarlyIfConversion() const override { return true; }
376 
377   /// Scheduling customization.
378   bool enableMachineScheduler() const override;
379   /// Pipeliner customization.
380   bool enableMachinePipeliner() const override;
381   /// Machine Pipeliner customization
382   bool useDFAforSMS() const override;
383   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
384   bool enablePostRAScheduler() const override;
385   AntiDepBreakMode getAntiDepBreakMode() const override;
386   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
387 
388   void overrideSchedPolicy(MachineSchedPolicy &Policy,
389                            unsigned NumRegionInstrs) const override;
390   bool useAA() const override;
391 
392   bool enableSubRegLiveness() const override;
393 
394   /// True if the GV will be accessed via an indirect symbol.
395   bool isGVIndirectSymbol(const GlobalValue *GV) const;
396 
397   /// True if the ABI is descriptor based.
398   bool usesFunctionDescriptors() const {
399     // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
400     // v1 ABI uses descriptors.
401     return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
402   }
403 
404   unsigned descriptorTOCAnchorOffset() const {
405     assert(usesFunctionDescriptors() &&
406            "Should only be called when the target uses descriptors.");
407     return IsPPC64 ? 8 : 4;
408   }
409 
410   unsigned descriptorEnvironmentPointerOffset() const {
411     assert(usesFunctionDescriptors() &&
412            "Should only be called when the target uses descriptors.");
413     return IsPPC64 ? 16 : 8;
414   }
415 
416   MCRegister getEnvironmentPointerRegister() const {
417     assert(usesFunctionDescriptors() &&
418            "Should only be called when the target uses descriptors.");
419      return IsPPC64 ? PPC::X11 : PPC::R11;
420   }
421 
422   MCRegister getTOCPointerRegister() const {
423     assert((is64BitELFABI() || isAIXABI()) &&
424            "Should only be called when the target is a TOC based ABI.");
425     return IsPPC64 ? PPC::X2 : PPC::R2;
426   }
427 
428   MCRegister getStackPointerRegister() const {
429     return IsPPC64 ? PPC::X1 : PPC::R1;
430   }
431 
432   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
433 
434   bool isPredictableSelectIsExpensive() const {
435     return PredictableSelectIsExpensive;
436   }
437 
438   // Select allocation orders of GPRC and G8RC. It should be strictly consistent
439   // with corresponding AltOrders in PPCRegisterInfo.td.
440   unsigned getGPRAllocationOrderIdx() const {
441     if (is64BitELFABI())
442       return 1;
443     if (isAIXABI())
444       return 2;
445     return 0;
446   }
447 
448   // GlobalISEL
449   const CallLowering *getCallLowering() const override;
450   const RegisterBankInfo *getRegBankInfo() const override;
451   const LegalizerInfo *getLegalizerInfo() const override;
452   InstructionSelector *getInstructionSelector() const override;
453 };
454 } // End llvm namespace
455 
456 #endif
457