xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCSubtarget.h (revision 5e801ac66d24704442eba426ed13c3effb8a34e7) 
1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
21 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
22 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
23 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/MC/MCInstrItineraries.h"
27 #include <string>
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "PPCGenSubtargetInfo.inc"
31 
32 // GCC #defines PPC on Linux but we use it as our namespace name
33 #undef PPC
34 
35 namespace llvm {
36 class StringRef;
37 
38 namespace PPC {
39   // -m directive values.
40 enum {
41   DIR_NONE,
42   DIR_32,
43   DIR_440,
44   DIR_601,
45   DIR_602,
46   DIR_603,
47   DIR_7400,
48   DIR_750,
49   DIR_970,
50   DIR_A2,
51   DIR_E500,
52   DIR_E500mc,
53   DIR_E5500,
54   DIR_PWR3,
55   DIR_PWR4,
56   DIR_PWR5,
57   DIR_PWR5X,
58   DIR_PWR6,
59   DIR_PWR6X,
60   DIR_PWR7,
61   DIR_PWR8,
62   DIR_PWR9,
63   DIR_PWR10,
64   DIR_PWR_FUTURE,
65   DIR_64
66 };
67 }
68 
69 class GlobalValue;
70 
71 class PPCSubtarget : public PPCGenSubtargetInfo {
72 public:
73   enum POPCNTDKind {
74     POPCNTD_Unavailable,
75     POPCNTD_Slow,
76     POPCNTD_Fast
77   };
78 
79 protected:
80   /// TargetTriple - What processor and OS we're targeting.
81   Triple TargetTriple;
82 
83   /// stackAlignment - The minimum alignment known to hold of the stack frame on
84   /// entry to the function and which must be maintained by every function.
85   Align StackAlignment;
86 
87   /// Selected instruction itineraries (one entry per itinerary class.)
88   InstrItineraryData InstrItins;
89 
90   /// Which cpu directive was used.
91   unsigned CPUDirective;
92 
93   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
94   bool HasMFOCRF;
95   bool Has64BitSupport;
96   bool Use64BitRegs;
97   bool UseCRBits;
98   bool HasHardFloat;
99   bool IsPPC64;
100   bool HasAltivec;
101   bool HasFPU;
102   bool HasSPE;
103   bool HasEFPU2;
104   bool HasVSX;
105   bool NeedsTwoConstNR;
106   bool HasP8Vector;
107   bool HasP8Altivec;
108   bool HasP8Crypto;
109   bool HasP9Vector;
110   bool HasP9Altivec;
111   bool HasP10Vector;
112   bool HasPrefixInstrs;
113   bool HasPCRelativeMemops;
114   bool HasMMA;
115   bool HasROPProtect;
116   bool HasPrivileged;
117   bool HasFCPSGN;
118   bool HasFSQRT;
119   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
120   bool HasRecipPrec;
121   bool HasSTFIWX;
122   bool HasLFIWAX;
123   bool HasFPRND;
124   bool HasFPCVT;
125   bool HasISEL;
126   bool HasBPERMD;
127   bool HasExtDiv;
128   bool HasCMPB;
129   bool HasLDBRX;
130   bool IsBookE;
131   bool HasOnlyMSYNC;
132   bool IsE500;
133   bool IsPPC4xx;
134   bool IsPPC6xx;
135   bool FeatureMFTB;
136   bool AllowsUnalignedFPAccess;
137   bool DeprecatedDST;
138   bool IsLittleEndian;
139   bool HasICBT;
140   bool HasInvariantFunctionDescriptors;
141   bool HasPartwordAtomics;
142   bool HasQuadwordAtomics;
143   bool HasDirectMove;
144   bool HasHTM;
145   bool HasFloat128;
146   bool HasFusion;
147   bool HasStoreFusion;
148   bool HasAddiLoadFusion;
149   bool HasAddisLoadFusion;
150   bool HasArithAddFusion;
151   bool HasAddLogicalFusion;
152   bool HasLogicalAddFusion;
153   bool HasLogicalFusion;
154   bool IsISA2_06;
155   bool IsISA2_07;
156   bool IsISA3_0;
157   bool IsISA3_1;
158   bool UseLongCalls;
159   bool SecurePlt;
160   bool VectorsUseTwoUnits;
161   bool UsePPCPreRASchedStrategy;
162   bool UsePPCPostRASchedStrategy;
163   bool PairedVectorMemops;
164   bool PredictableSelectIsExpensive;
165   bool HasModernAIXAs;
166   bool IsAIX;
167 
168   POPCNTDKind HasPOPCNTD;
169 
170   const PPCTargetMachine &TM;
171   PPCFrameLowering FrameLowering;
172   PPCInstrInfo InstrInfo;
173   PPCTargetLowering TLInfo;
174   SelectionDAGTargetInfo TSInfo;
175 
176   /// GlobalISel related APIs.
177   std::unique_ptr<CallLowering> CallLoweringInfo;
178   std::unique_ptr<LegalizerInfo> Legalizer;
179   std::unique_ptr<RegisterBankInfo> RegBankInfo;
180   std::unique_ptr<InstructionSelector> InstSelector;
181 
182 public:
183   /// This constructor initializes the data members to match that
184   /// of the specified triple.
185   ///
186   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
187                const PPCTargetMachine &TM);
188 
189   /// ParseSubtargetFeatures - Parses features string setting specified
190   /// subtarget options.  Definition of function is auto generated by tblgen.
191   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
192 
193   /// getStackAlignment - Returns the minimum alignment known to hold of the
194   /// stack frame on entry to the function and which must be maintained by every
195   /// function for this subtarget.
196   Align getStackAlignment() const { return StackAlignment; }
197 
198   /// getCPUDirective - Returns the -m directive specified for the cpu.
199   ///
200   unsigned getCPUDirective() const { return CPUDirective; }
201 
202   /// getInstrItins - Return the instruction itineraries based on subtarget
203   /// selection.
204   const InstrItineraryData *getInstrItineraryData() const override {
205     return &InstrItins;
206   }
207 
208   const PPCFrameLowering *getFrameLowering() const override {
209     return &FrameLowering;
210   }
211   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
212   const PPCTargetLowering *getTargetLowering() const override {
213     return &TLInfo;
214   }
215   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
216     return &TSInfo;
217   }
218   const PPCRegisterInfo *getRegisterInfo() const override {
219     return &getInstrInfo()->getRegisterInfo();
220   }
221   const PPCTargetMachine &getTargetMachine() const { return TM; }
222 
223   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
224   /// so that we can use initializer lists for subtarget initialization.
225   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
226 
227 private:
228   void initializeEnvironment();
229   void initSubtargetFeatures(StringRef CPU, StringRef FS);
230 
231 public:
232   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
233   ///
234   bool isPPC64() const;
235 
236   /// has64BitSupport - Return true if the selected CPU supports 64-bit
237   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
238   bool has64BitSupport() const { return Has64BitSupport; }
239   // useSoftFloat - Return true if soft-float option is turned on.
240   bool useSoftFloat() const {
241     if (isAIXABI() && !HasHardFloat)
242       report_fatal_error("soft-float is not yet supported on AIX.");
243     return !HasHardFloat;
244   }
245 
246   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
247   /// registers in 32-bit mode when possible.  This can only true if
248   /// has64BitSupport() returns true.
249   bool use64BitRegs() const { return Use64BitRegs; }
250 
251   /// useCRBits - Return true if we should store and manipulate i1 values in
252   /// the individual condition register bits.
253   bool useCRBits() const { return UseCRBits; }
254 
255   // isLittleEndian - True if generating little-endian code
256   bool isLittleEndian() const { return IsLittleEndian; }
257 
258   // Specific obvious features.
259   bool hasFCPSGN() const { return HasFCPSGN; }
260   bool hasFSQRT() const { return HasFSQRT; }
261   bool hasFRE() const { return HasFRE; }
262   bool hasFRES() const { return HasFRES; }
263   bool hasFRSQRTE() const { return HasFRSQRTE; }
264   bool hasFRSQRTES() const { return HasFRSQRTES; }
265   bool hasRecipPrec() const { return HasRecipPrec; }
266   bool hasSTFIWX() const { return HasSTFIWX; }
267   bool hasLFIWAX() const { return HasLFIWAX; }
268   bool hasFPRND() const { return HasFPRND; }
269   bool hasFPCVT() const { return HasFPCVT; }
270   bool hasAltivec() const { return HasAltivec; }
271   bool hasSPE() const { return HasSPE; }
272   bool hasEFPU2() const { return HasEFPU2; }
273   bool hasFPU() const { return HasFPU; }
274   bool hasVSX() const { return HasVSX; }
275   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
276   bool hasP8Vector() const { return HasP8Vector; }
277   bool hasP8Altivec() const { return HasP8Altivec; }
278   bool hasP8Crypto() const { return HasP8Crypto; }
279   bool hasP9Vector() const { return HasP9Vector; }
280   bool hasP9Altivec() const { return HasP9Altivec; }
281   bool hasP10Vector() const { return HasP10Vector; }
282   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
283   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
284   bool hasMMA() const { return HasMMA; }
285   bool hasROPProtect() const { return HasROPProtect; }
286   bool hasPrivileged() const { return HasPrivileged; }
287   bool pairedVectorMemops() const { return PairedVectorMemops; }
288   bool hasMFOCRF() const { return HasMFOCRF; }
289   bool hasISEL() const { return HasISEL; }
290   bool hasBPERMD() const { return HasBPERMD; }
291   bool hasExtDiv() const { return HasExtDiv; }
292   bool hasCMPB() const { return HasCMPB; }
293   bool hasLDBRX() const { return HasLDBRX; }
294   bool isBookE() const { return IsBookE; }
295   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
296   bool isPPC4xx() const { return IsPPC4xx; }
297   bool isPPC6xx() const { return IsPPC6xx; }
298   bool isSecurePlt() const {return SecurePlt; }
299   bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
300   bool isE500() const { return IsE500; }
301   bool isFeatureMFTB() const { return FeatureMFTB; }
302   bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
303   bool isDeprecatedDST() const { return DeprecatedDST; }
304   bool hasICBT() const { return HasICBT; }
305   bool hasInvariantFunctionDescriptors() const {
306     return HasInvariantFunctionDescriptors;
307   }
308   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
309   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
310   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
311   bool hasQuadwordAtomics() const { return HasQuadwordAtomics; }
312   bool hasDirectMove() const { return HasDirectMove; }
313 
314   Align getPlatformStackAlignment() const {
315     return Align(16);
316   }
317 
318   unsigned  getRedZoneSize() const {
319     if (isPPC64())
320       // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
321       return 288;
322 
323     // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
324     // PPC32 SVR4ABI has no redzone.
325     return isAIXABI() ? 220 : 0;
326   }
327 
328   bool hasHTM() const { return HasHTM; }
329   bool hasFloat128() const { return HasFloat128; }
330   bool isISA2_06() const { return IsISA2_06; }
331   bool isISA2_07() const { return IsISA2_07; }
332   bool isISA3_0() const { return IsISA3_0; }
333   bool isISA3_1() const { return IsISA3_1; }
334   bool useLongCalls() const { return UseLongCalls; }
335   bool hasFusion() const { return HasFusion; }
336   bool hasStoreFusion() const { return HasStoreFusion; }
337   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
338   bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
339   bool hasArithAddFusion() const { return HasArithAddFusion; }
340   bool hasAddLogicalFusion() const { return HasAddLogicalFusion; }
341   bool hasLogicalAddFusion() const { return HasLogicalAddFusion; }
342   bool hasLogicalFusion() const { return HasLogicalFusion; }
343   bool needsSwapsForVSXMemOps() const {
344     return hasVSX() && isLittleEndian() && !hasP9Vector();
345   }
346 
347   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
348 
349   const Triple &getTargetTriple() const { return TargetTriple; }
350 
351   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
352   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
353   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
354 
355   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
356   bool isSVR4ABI() const { return !isAIXABI(); }
357   bool isELFv2ABI() const;
358 
359   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
360   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
361   bool isUsingPCRelativeCalls() const;
362 
363   /// Originally, this function return hasISEL(). Now we always enable it,
364   /// but may expand the ISEL instruction later.
365   bool enableEarlyIfConversion() const override { return true; }
366 
367   /// Scheduling customization.
368   bool enableMachineScheduler() const override;
369   /// Pipeliner customization.
370   bool enableMachinePipeliner() const override;
371   /// Machine Pipeliner customization
372   bool useDFAforSMS() const override;
373   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
374   bool enablePostRAScheduler() const override;
375   AntiDepBreakMode getAntiDepBreakMode() const override;
376   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
377 
378   void overrideSchedPolicy(MachineSchedPolicy &Policy,
379                            unsigned NumRegionInstrs) const override;
380   bool useAA() const override;
381 
382   bool enableSubRegLiveness() const override;
383 
384   /// True if the GV will be accessed via an indirect symbol.
385   bool isGVIndirectSymbol(const GlobalValue *GV) const;
386 
387   /// True if the ABI is descriptor based.
388   bool usesFunctionDescriptors() const {
389     // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
390     // v1 ABI uses descriptors.
391     return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
392   }
393 
394   unsigned descriptorTOCAnchorOffset() const {
395     assert(usesFunctionDescriptors() &&
396            "Should only be called when the target uses descriptors.");
397     return IsPPC64 ? 8 : 4;
398   }
399 
400   unsigned descriptorEnvironmentPointerOffset() const {
401     assert(usesFunctionDescriptors() &&
402            "Should only be called when the target uses descriptors.");
403     return IsPPC64 ? 16 : 8;
404   }
405 
406   MCRegister getEnvironmentPointerRegister() const {
407     assert(usesFunctionDescriptors() &&
408            "Should only be called when the target uses descriptors.");
409      return IsPPC64 ? PPC::X11 : PPC::R11;
410   }
411 
412   MCRegister getTOCPointerRegister() const {
413     assert((is64BitELFABI() || isAIXABI()) &&
414            "Should only be called when the target is a TOC based ABI.");
415     return IsPPC64 ? PPC::X2 : PPC::R2;
416   }
417 
418   MCRegister getStackPointerRegister() const {
419     return IsPPC64 ? PPC::X1 : PPC::R1;
420   }
421 
422   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
423 
424   bool isPredictableSelectIsExpensive() const {
425     return PredictableSelectIsExpensive;
426   }
427 
428   // Select allocation orders of GPRC and G8RC. It should be strictly consistent
429   // with corresponding AltOrders in PPCRegisterInfo.td.
430   unsigned getGPRAllocationOrderIdx() const {
431     if (is64BitELFABI())
432       return 1;
433     if (isAIXABI())
434       return 2;
435     return 0;
436   }
437 
438   // GlobalISEL
439   const CallLowering *getCallLowering() const override;
440   const RegisterBankInfo *getRegBankInfo() const override;
441   const LegalizerInfo *getLegalizerInfo() const override;
442   InstructionSelector *getInstructionSelector() const override;
443 };
444 } // End llvm namespace
445 
446 #endif
447