1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPC specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCSubtarget.h" 14 #include "PPC.h" 15 #include "PPCRegisterInfo.h" 16 #include "PPCTargetMachine.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineScheduler.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/IR/GlobalValue.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Target/TargetMachine.h" 25 #include <cstdlib> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "ppc-subtarget" 30 31 #define GET_SUBTARGETINFO_TARGET_DESC 32 #define GET_SUBTARGETINFO_CTOR 33 #include "PPCGenSubtargetInfo.inc" 34 35 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 36 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 37 38 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned", 39 cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"), 40 cl::Hidden); 41 42 static cl::opt<bool> 43 EnableMachinePipeliner("ppc-enable-pipeliner", 44 cl::desc("Enable Machine Pipeliner for PPC"), 45 cl::init(false), cl::Hidden); 46 47 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 48 StringRef FS) { 49 initializeEnvironment(); 50 initSubtargetFeatures(CPU, FS); 51 return *this; 52 } 53 54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, 55 const std::string &FS, const PPCTargetMachine &TM) 56 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 57 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 58 TargetTriple.getArch() == Triple::ppc64le), 59 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), 60 InstrInfo(*this), TLInfo(TM, *this) {} 61 62 void PPCSubtarget::initializeEnvironment() { 63 StackAlignment = Align(16); 64 CPUDirective = PPC::DIR_NONE; 65 HasMFOCRF = false; 66 Has64BitSupport = false; 67 Use64BitRegs = false; 68 UseCRBits = false; 69 HasHardFloat = false; 70 HasAltivec = false; 71 HasSPE = false; 72 HasFPU = false; 73 HasQPX = false; 74 HasVSX = false; 75 NeedsTwoConstNR = false; 76 HasP8Vector = false; 77 HasP8Altivec = false; 78 HasP8Crypto = false; 79 HasP9Vector = false; 80 HasP9Altivec = false; 81 HasP10Vector = false; 82 HasPrefixInstrs = false; 83 HasPCRelativeMemops = false; 84 HasFCPSGN = false; 85 HasFSQRT = false; 86 HasFRE = false; 87 HasFRES = false; 88 HasFRSQRTE = false; 89 HasFRSQRTES = false; 90 HasRecipPrec = false; 91 HasSTFIWX = false; 92 HasLFIWAX = false; 93 HasFPRND = false; 94 HasFPCVT = false; 95 HasISEL = false; 96 HasBPERMD = false; 97 HasExtDiv = false; 98 HasCMPB = false; 99 HasLDBRX = false; 100 IsBookE = false; 101 HasOnlyMSYNC = false; 102 IsPPC4xx = false; 103 IsPPC6xx = false; 104 IsE500 = false; 105 FeatureMFTB = false; 106 AllowsUnalignedFPAccess = false; 107 DeprecatedDST = false; 108 HasICBT = false; 109 HasInvariantFunctionDescriptors = false; 110 HasPartwordAtomics = false; 111 HasDirectMove = false; 112 IsQPXStackUnaligned = false; 113 HasHTM = false; 114 HasFloat128 = false; 115 HasFusion = false; 116 HasAddiLoadFusion = false; 117 HasAddisLoadFusion = false; 118 IsISA3_0 = false; 119 IsISA3_1 = false; 120 UseLongCalls = false; 121 SecurePlt = false; 122 VectorsUseTwoUnits = false; 123 UsePPCPreRASchedStrategy = false; 124 UsePPCPostRASchedStrategy = false; 125 PredictableSelectIsExpensive = false; 126 127 HasPOPCNTD = POPCNTD_Unavailable; 128 } 129 130 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 131 // Determine default and user specified characteristics 132 std::string CPUName = std::string(CPU); 133 if (CPUName.empty() || CPU == "generic") { 134 // If cross-compiling with -march=ppc64le without -mcpu 135 if (TargetTriple.getArch() == Triple::ppc64le) 136 CPUName = "ppc64le"; 137 else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe) 138 CPUName = "e500"; 139 else 140 CPUName = "generic"; 141 } 142 143 // Initialize scheduling itinerary for the specified CPU. 144 InstrItins = getInstrItineraryForCPU(CPUName); 145 146 // Parse features string. 147 ParseSubtargetFeatures(CPUName, FS); 148 149 // If the user requested use of 64-bit regs, but the cpu selected doesn't 150 // support it, ignore. 151 if (IsPPC64 && has64BitSupport()) 152 Use64BitRegs = true; 153 154 if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) || 155 TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() || 156 TargetTriple.isMusl()) 157 SecurePlt = true; 158 159 if (HasSPE && IsPPC64) 160 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false); 161 if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU)) 162 report_fatal_error( 163 "SPE and traditional floating point cannot both be enabled.\n", false); 164 165 // If not SPE, set standard FPU 166 if (!HasSPE) 167 HasFPU = true; 168 169 // QPX requires a 32-byte aligned stack. Note that we need to do this if 170 // we're compiling for a BG/Q system regardless of whether or not QPX 171 // is enabled because external functions will assume this alignment. 172 IsQPXStackUnaligned = QPXStackUnaligned; 173 StackAlignment = getPlatformStackAlignment(); 174 175 // Determine endianness. 176 // FIXME: Part of the TargetMachine. 177 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 178 } 179 180 bool PPCSubtarget::enableMachineScheduler() const { return true; } 181 182 bool PPCSubtarget::enableMachinePipeliner() const { 183 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; 184 } 185 186 bool PPCSubtarget::useDFAforSMS() const { return false; } 187 188 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 189 bool PPCSubtarget::enablePostRAScheduler() const { return true; } 190 191 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 192 return TargetSubtargetInfo::ANTIDEP_ALL; 193 } 194 195 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 196 CriticalPathRCs.clear(); 197 CriticalPathRCs.push_back(isPPC64() ? 198 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 199 } 200 201 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 202 unsigned NumRegionInstrs) const { 203 // The GenericScheduler that we use defaults to scheduling bottom up only. 204 // We want to schedule from both the top and the bottom and so we set 205 // OnlyBottomUp to false. 206 // We want to do bi-directional scheduling since it provides a more balanced 207 // schedule leading to better performance. 208 Policy.OnlyBottomUp = false; 209 // Spilling is generally expensive on all PPC cores, so always enable 210 // register-pressure tracking. 211 Policy.ShouldTrackPressure = true; 212 } 213 214 bool PPCSubtarget::useAA() const { 215 return true; 216 } 217 218 bool PPCSubtarget::enableSubRegLiveness() const { 219 return UseSubRegLiveness; 220 } 221 222 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { 223 // Large code model always uses the TOC even for local symbols. 224 if (TM.getCodeModel() == CodeModel::Large) 225 return true; 226 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 227 return false; 228 return true; 229 } 230 231 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 232 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 233 234 bool PPCSubtarget::isUsingPCRelativeCalls() const { 235 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() && 236 CodeModel::Medium == getTargetMachine().getCodeModel(); 237 } 238