1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPC specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCSubtarget.h" 14 #include "GISel/PPCCallLowering.h" 15 #include "GISel/PPCLegalizerInfo.h" 16 #include "GISel/PPCRegisterBankInfo.h" 17 #include "PPC.h" 18 #include "PPCRegisterInfo.h" 19 #include "PPCTargetMachine.h" 20 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineScheduler.h" 23 #include "llvm/IR/Attributes.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/IR/GlobalValue.h" 26 #include "llvm/Support/CommandLine.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Target/TargetMachine.h" 29 #include <cstdlib> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "ppc-subtarget" 34 35 #define GET_SUBTARGETINFO_TARGET_DESC 36 #define GET_SUBTARGETINFO_CTOR 37 #include "PPCGenSubtargetInfo.inc" 38 39 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 40 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 41 42 static cl::opt<bool> 43 EnableMachinePipeliner("ppc-enable-pipeliner", 44 cl::desc("Enable Machine Pipeliner for PPC"), 45 cl::init(false), cl::Hidden); 46 47 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 48 StringRef FS) { 49 initializeEnvironment(); 50 initSubtargetFeatures(CPU, FS); 51 return *this; 52 } 53 54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, 55 const std::string &FS, const PPCTargetMachine &TM) 56 : PPCGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT), 57 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 58 TargetTriple.getArch() == Triple::ppc64le), 59 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), 60 InstrInfo(*this), TLInfo(TM, *this) { 61 CallLoweringInfo.reset(new PPCCallLowering(*getTargetLowering())); 62 Legalizer.reset(new PPCLegalizerInfo(*this)); 63 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo()); 64 RegBankInfo.reset(RBI); 65 66 InstSelector.reset(createPPCInstructionSelector( 67 *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI)); 68 } 69 70 void PPCSubtarget::initializeEnvironment() { 71 StackAlignment = Align(16); 72 CPUDirective = PPC::DIR_NONE; 73 HasMFOCRF = false; 74 Has64BitSupport = false; 75 Use64BitRegs = false; 76 UseCRBits = false; 77 HasHardFloat = false; 78 HasAltivec = false; 79 HasSPE = false; 80 HasEFPU2 = false; 81 HasFPU = false; 82 HasVSX = false; 83 NeedsTwoConstNR = false; 84 HasP8Vector = false; 85 HasP8Altivec = false; 86 HasP8Crypto = false; 87 HasP9Vector = false; 88 HasP9Altivec = false; 89 HasMMA = false; 90 HasP10Vector = false; 91 HasPrefixInstrs = false; 92 HasPCRelativeMemops = false; 93 HasFCPSGN = false; 94 HasFSQRT = false; 95 HasFRE = false; 96 HasFRES = false; 97 HasFRSQRTE = false; 98 HasFRSQRTES = false; 99 HasRecipPrec = false; 100 HasSTFIWX = false; 101 HasLFIWAX = false; 102 HasFPRND = false; 103 HasFPCVT = false; 104 HasISEL = false; 105 HasBPERMD = false; 106 HasExtDiv = false; 107 HasCMPB = false; 108 HasLDBRX = false; 109 IsBookE = false; 110 HasOnlyMSYNC = false; 111 IsPPC4xx = false; 112 IsPPC6xx = false; 113 IsE500 = false; 114 FeatureMFTB = false; 115 AllowsUnalignedFPAccess = false; 116 DeprecatedDST = false; 117 HasICBT = false; 118 HasInvariantFunctionDescriptors = false; 119 HasPartwordAtomics = false; 120 HasDirectMove = false; 121 HasHTM = false; 122 HasFloat128 = false; 123 HasFusion = false; 124 HasStoreFusion = false; 125 HasAddiLoadFusion = false; 126 HasAddisLoadFusion = false; 127 IsISA3_0 = false; 128 IsISA3_1 = false; 129 UseLongCalls = false; 130 SecurePlt = false; 131 VectorsUseTwoUnits = false; 132 UsePPCPreRASchedStrategy = false; 133 UsePPCPostRASchedStrategy = false; 134 PairedVectorMemops = false; 135 PredictableSelectIsExpensive = false; 136 HasModernAIXAs = false; 137 IsAIX = false; 138 139 HasPOPCNTD = POPCNTD_Unavailable; 140 } 141 142 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 143 // Determine default and user specified characteristics 144 std::string CPUName = std::string(CPU); 145 if (CPUName.empty() || CPU == "generic") { 146 // If cross-compiling with -march=ppc64le without -mcpu 147 if (TargetTriple.getArch() == Triple::ppc64le) 148 CPUName = "ppc64le"; 149 else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe) 150 CPUName = "e500"; 151 else 152 CPUName = "generic"; 153 } 154 155 // Initialize scheduling itinerary for the specified CPU. 156 InstrItins = getInstrItineraryForCPU(CPUName); 157 158 // Parse features string. 159 ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS); 160 161 // If the user requested use of 64-bit regs, but the cpu selected doesn't 162 // support it, ignore. 163 if (IsPPC64 && has64BitSupport()) 164 Use64BitRegs = true; 165 166 if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) || 167 TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() || 168 TargetTriple.isMusl()) 169 SecurePlt = true; 170 171 if (HasSPE && IsPPC64) 172 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false); 173 if (HasSPE && (HasAltivec || HasVSX || HasFPU)) 174 report_fatal_error( 175 "SPE and traditional floating point cannot both be enabled.\n", false); 176 177 // If not SPE, set standard FPU 178 if (!HasSPE) 179 HasFPU = true; 180 181 StackAlignment = getPlatformStackAlignment(); 182 183 // Determine endianness. 184 // FIXME: Part of the TargetMachine. 185 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le || 186 TargetTriple.getArch() == Triple::ppcle); 187 } 188 189 bool PPCSubtarget::enableMachineScheduler() const { return true; } 190 191 bool PPCSubtarget::enableMachinePipeliner() const { 192 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; 193 } 194 195 bool PPCSubtarget::useDFAforSMS() const { return false; } 196 197 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 198 bool PPCSubtarget::enablePostRAScheduler() const { return true; } 199 200 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 201 return TargetSubtargetInfo::ANTIDEP_ALL; 202 } 203 204 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 205 CriticalPathRCs.clear(); 206 CriticalPathRCs.push_back(isPPC64() ? 207 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 208 } 209 210 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 211 unsigned NumRegionInstrs) const { 212 // The GenericScheduler that we use defaults to scheduling bottom up only. 213 // We want to schedule from both the top and the bottom and so we set 214 // OnlyBottomUp to false. 215 // We want to do bi-directional scheduling since it provides a more balanced 216 // schedule leading to better performance. 217 Policy.OnlyBottomUp = false; 218 // Spilling is generally expensive on all PPC cores, so always enable 219 // register-pressure tracking. 220 Policy.ShouldTrackPressure = true; 221 } 222 223 bool PPCSubtarget::useAA() const { 224 return true; 225 } 226 227 bool PPCSubtarget::enableSubRegLiveness() const { 228 return UseSubRegLiveness; 229 } 230 231 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { 232 // Large code model always uses the TOC even for local symbols. 233 if (TM.getCodeModel() == CodeModel::Large) 234 return true; 235 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 236 return false; 237 return true; 238 } 239 240 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 241 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 242 243 bool PPCSubtarget::isUsingPCRelativeCalls() const { 244 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() && 245 CodeModel::Medium == getTargetMachine().getCodeModel(); 246 } 247 248 // GlobalISEL 249 const CallLowering *PPCSubtarget::getCallLowering() const { 250 return CallLoweringInfo.get(); 251 } 252 253 const RegisterBankInfo *PPCSubtarget::getRegBankInfo() const { 254 return RegBankInfo.get(); 255 } 256 257 const LegalizerInfo *PPCSubtarget::getLegalizerInfo() const { 258 return Legalizer.get(); 259 } 260 261 InstructionSelector *PPCSubtarget::getInstructionSelector() const { 262 return InstSelector.get(); 263 } 264