1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPC specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCSubtarget.h" 14 #include "GISel/PPCCallLowering.h" 15 #include "GISel/PPCLegalizerInfo.h" 16 #include "GISel/PPCRegisterBankInfo.h" 17 #include "PPC.h" 18 #include "PPCRegisterInfo.h" 19 #include "PPCTargetMachine.h" 20 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineScheduler.h" 24 #include "llvm/IR/Attributes.h" 25 #include "llvm/IR/Function.h" 26 #include "llvm/IR/GlobalValue.h" 27 #include "llvm/MC/TargetRegistry.h" 28 #include "llvm/Support/CommandLine.h" 29 #include "llvm/Target/TargetMachine.h" 30 #include <cstdlib> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "ppc-subtarget" 35 36 #define GET_SUBTARGETINFO_TARGET_DESC 37 #define GET_SUBTARGETINFO_CTOR 38 #include "PPCGenSubtargetInfo.inc" 39 40 static cl::opt<bool> 41 UseSubRegLiveness("ppc-track-subreg-liveness", 42 cl::desc("Enable subregister liveness tracking for PPC"), 43 cl::init(true), cl::Hidden); 44 45 static cl::opt<bool> 46 EnableMachinePipeliner("ppc-enable-pipeliner", 47 cl::desc("Enable Machine Pipeliner for PPC"), 48 cl::init(false), cl::Hidden); 49 50 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 51 StringRef TuneCPU, 52 StringRef FS) { 53 initializeEnvironment(); 54 initSubtargetFeatures(CPU, TuneCPU, FS); 55 return *this; 56 } 57 58 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, 59 const std::string &TuneCPU, const std::string &FS, 60 const PPCTargetMachine &TM) 61 : PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS), TargetTriple(TT), 62 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 63 TargetTriple.getArch() == Triple::ppc64le), 64 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)), 65 InstrInfo(*this), TLInfo(TM, *this) { 66 CallLoweringInfo.reset(new PPCCallLowering(*getTargetLowering())); 67 Legalizer.reset(new PPCLegalizerInfo(*this)); 68 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo()); 69 RegBankInfo.reset(RBI); 70 71 InstSelector.reset(createPPCInstructionSelector( 72 *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI)); 73 } 74 75 void PPCSubtarget::initializeEnvironment() { 76 StackAlignment = Align(16); 77 CPUDirective = PPC::DIR_NONE; 78 HasPOPCNTD = POPCNTD_Unavailable; 79 } 80 81 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, 82 StringRef FS) { 83 // Determine default and user specified characteristics 84 std::string CPUName = std::string(CPU); 85 if (CPUName.empty() || CPU == "generic") { 86 // If cross-compiling with -march=ppc64le without -mcpu 87 if (TargetTriple.getArch() == Triple::ppc64le) 88 CPUName = "ppc64le"; 89 else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe) 90 CPUName = "e500"; 91 else 92 CPUName = "generic"; 93 } 94 95 // Determine the CPU to schedule for. 96 if (TuneCPU.empty()) TuneCPU = CPUName; 97 98 // Initialize scheduling itinerary for the specified CPU. 99 InstrItins = getInstrItineraryForCPU(CPUName); 100 101 // Parse features string. 102 ParseSubtargetFeatures(CPUName, TuneCPU, FS); 103 104 // If the user requested use of 64-bit regs, but the cpu selected doesn't 105 // support it, ignore. 106 if (IsPPC64 && has64BitSupport()) 107 Use64BitRegs = true; 108 109 if (TargetTriple.isPPC32SecurePlt()) 110 IsSecurePlt = true; 111 112 if (HasSPE && IsPPC64) 113 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false); 114 if (HasSPE && (HasAltivec || HasVSX || HasFPU)) 115 report_fatal_error( 116 "SPE and traditional floating point cannot both be enabled.\n", false); 117 118 // If not SPE, set standard FPU 119 if (!HasSPE) 120 HasFPU = true; 121 122 StackAlignment = getPlatformStackAlignment(); 123 124 // Determine endianness. 125 IsLittleEndian = TM.isLittleEndian(); 126 127 if (HasAIXSmallLocalExecTLS && (!TargetTriple.isOSAIX() || !IsPPC64)) 128 report_fatal_error( 129 "The aix-small-local-exec-tls attribute is only supported on AIX in " 130 "64-bit mode.\n", false); 131 } 132 133 bool PPCSubtarget::enableMachineScheduler() const { return true; } 134 135 bool PPCSubtarget::enableMachinePipeliner() const { 136 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; 137 } 138 139 bool PPCSubtarget::useDFAforSMS() const { return false; } 140 141 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 142 bool PPCSubtarget::enablePostRAScheduler() const { return true; } 143 144 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 145 return TargetSubtargetInfo::ANTIDEP_ALL; 146 } 147 148 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 149 CriticalPathRCs.clear(); 150 CriticalPathRCs.push_back(isPPC64() ? 151 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 152 } 153 154 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 155 unsigned NumRegionInstrs) const { 156 // The GenericScheduler that we use defaults to scheduling bottom up only. 157 // We want to schedule from both the top and the bottom and so we set 158 // OnlyBottomUp to false. 159 // We want to do bi-directional scheduling since it provides a more balanced 160 // schedule leading to better performance. 161 Policy.OnlyBottomUp = false; 162 // Spilling is generally expensive on all PPC cores, so always enable 163 // register-pressure tracking. 164 Policy.ShouldTrackPressure = true; 165 } 166 167 bool PPCSubtarget::useAA() const { 168 return true; 169 } 170 171 bool PPCSubtarget::enableSubRegLiveness() const { 172 return UseSubRegLiveness; 173 } 174 175 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { 176 // Large code model always uses the TOC even for local symbols. 177 if (TM.getCodeModel() == CodeModel::Large) 178 return true; 179 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 180 return false; 181 return true; 182 } 183 184 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 185 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 186 187 bool PPCSubtarget::isUsingPCRelativeCalls() const { 188 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() && 189 CodeModel::Medium == getTargetMachine().getCodeModel(); 190 } 191 192 // GlobalISEL 193 const CallLowering *PPCSubtarget::getCallLowering() const { 194 return CallLoweringInfo.get(); 195 } 196 197 const RegisterBankInfo *PPCSubtarget::getRegBankInfo() const { 198 return RegBankInfo.get(); 199 } 200 201 const LegalizerInfo *PPCSubtarget::getLegalizerInfo() const { 202 return Legalizer.get(); 203 } 204 205 InstructionSelector *PPCSubtarget::getInstructionSelector() const { 206 return InstSelector.get(); 207 } 208