1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPC specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCSubtarget.h" 14 #include "GISel/PPCCallLowering.h" 15 #include "GISel/PPCLegalizerInfo.h" 16 #include "GISel/PPCRegisterBankInfo.h" 17 #include "PPC.h" 18 #include "PPCRegisterInfo.h" 19 #include "PPCTargetMachine.h" 20 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineScheduler.h" 23 #include "llvm/IR/Attributes.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/IR/GlobalValue.h" 26 #include "llvm/MC/TargetRegistry.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Target/TargetMachine.h" 29 #include <cstdlib> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "ppc-subtarget" 34 35 #define GET_SUBTARGETINFO_TARGET_DESC 36 #define GET_SUBTARGETINFO_CTOR 37 #include "PPCGenSubtargetInfo.inc" 38 39 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 40 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 41 42 static cl::opt<bool> 43 EnableMachinePipeliner("ppc-enable-pipeliner", 44 cl::desc("Enable Machine Pipeliner for PPC"), 45 cl::init(false), cl::Hidden); 46 47 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 48 StringRef FS) { 49 initializeEnvironment(); 50 initSubtargetFeatures(CPU, FS); 51 return *this; 52 } 53 54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, 55 const std::string &FS, const PPCTargetMachine &TM) 56 : PPCGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT), 57 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 58 TargetTriple.getArch() == Triple::ppc64le), 59 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), 60 InstrInfo(*this), TLInfo(TM, *this) { 61 CallLoweringInfo.reset(new PPCCallLowering(*getTargetLowering())); 62 Legalizer.reset(new PPCLegalizerInfo(*this)); 63 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo()); 64 RegBankInfo.reset(RBI); 65 66 InstSelector.reset(createPPCInstructionSelector( 67 *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI)); 68 } 69 70 void PPCSubtarget::initializeEnvironment() { 71 StackAlignment = Align(16); 72 CPUDirective = PPC::DIR_NONE; 73 HasMFOCRF = false; 74 Has64BitSupport = false; 75 Use64BitRegs = false; 76 UseCRBits = false; 77 HasHardFloat = false; 78 HasAltivec = false; 79 HasSPE = false; 80 HasEFPU2 = false; 81 HasFPU = false; 82 HasVSX = false; 83 NeedsTwoConstNR = false; 84 HasP8Vector = false; 85 HasP8Altivec = false; 86 HasP8Crypto = false; 87 HasP9Vector = false; 88 HasP9Altivec = false; 89 HasMMA = false; 90 HasROPProtect = false; 91 HasPrivileged = false; 92 HasP10Vector = false; 93 HasPrefixInstrs = false; 94 HasPCRelativeMemops = false; 95 HasFCPSGN = false; 96 HasFSQRT = false; 97 HasFRE = false; 98 HasFRES = false; 99 HasFRSQRTE = false; 100 HasFRSQRTES = false; 101 HasRecipPrec = false; 102 HasSTFIWX = false; 103 HasLFIWAX = false; 104 HasFPRND = false; 105 HasFPCVT = false; 106 HasISEL = false; 107 HasBPERMD = false; 108 HasExtDiv = false; 109 HasCMPB = false; 110 HasLDBRX = false; 111 IsBookE = false; 112 HasOnlyMSYNC = false; 113 IsPPC4xx = false; 114 IsPPC6xx = false; 115 IsE500 = false; 116 FeatureMFTB = false; 117 AllowsUnalignedFPAccess = false; 118 DeprecatedDST = false; 119 HasICBT = false; 120 HasInvariantFunctionDescriptors = false; 121 HasPartwordAtomics = false; 122 HasQuadwordAtomics = false; 123 HasDirectMove = false; 124 HasHTM = false; 125 HasFloat128 = false; 126 HasFusion = false; 127 HasStoreFusion = false; 128 HasAddiLoadFusion = false; 129 HasAddisLoadFusion = false; 130 HasArithAddFusion = false; 131 HasAddLogicalFusion = false; 132 HasLogicalAddFusion = false; 133 HasLogicalFusion = false; 134 HasSha3Fusion = false; 135 HasCompareFusion = false; 136 HasWideImmFusion = false; 137 HasZeroMoveFusion = false; 138 HasBack2BackFusion = false; 139 IsISA2_06 = false; 140 IsISA2_07 = false; 141 IsISA3_0 = false; 142 IsISA3_1 = false; 143 UseLongCalls = false; 144 SecurePlt = false; 145 VectorsUseTwoUnits = false; 146 UsePPCPreRASchedStrategy = false; 147 UsePPCPostRASchedStrategy = false; 148 PairedVectorMemops = false; 149 PredictableSelectIsExpensive = false; 150 HasModernAIXAs = false; 151 IsAIX = false; 152 153 HasPOPCNTD = POPCNTD_Unavailable; 154 } 155 156 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 157 // Determine default and user specified characteristics 158 std::string CPUName = std::string(CPU); 159 if (CPUName.empty() || CPU == "generic") { 160 // If cross-compiling with -march=ppc64le without -mcpu 161 if (TargetTriple.getArch() == Triple::ppc64le) 162 CPUName = "ppc64le"; 163 else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe) 164 CPUName = "e500"; 165 else 166 CPUName = "generic"; 167 } 168 169 // Initialize scheduling itinerary for the specified CPU. 170 InstrItins = getInstrItineraryForCPU(CPUName); 171 172 // Parse features string. 173 ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS); 174 175 // If the user requested use of 64-bit regs, but the cpu selected doesn't 176 // support it, ignore. 177 if (IsPPC64 && has64BitSupport()) 178 Use64BitRegs = true; 179 180 if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) || 181 TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() || 182 TargetTriple.isMusl()) 183 SecurePlt = true; 184 185 if (HasSPE && IsPPC64) 186 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false); 187 if (HasSPE && (HasAltivec || HasVSX || HasFPU)) 188 report_fatal_error( 189 "SPE and traditional floating point cannot both be enabled.\n", false); 190 191 // If not SPE, set standard FPU 192 if (!HasSPE) 193 HasFPU = true; 194 195 StackAlignment = getPlatformStackAlignment(); 196 197 // Determine endianness. 198 IsLittleEndian = TM.isLittleEndian(); 199 } 200 201 bool PPCSubtarget::enableMachineScheduler() const { return true; } 202 203 bool PPCSubtarget::enableMachinePipeliner() const { 204 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; 205 } 206 207 bool PPCSubtarget::useDFAforSMS() const { return false; } 208 209 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 210 bool PPCSubtarget::enablePostRAScheduler() const { return true; } 211 212 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 213 return TargetSubtargetInfo::ANTIDEP_ALL; 214 } 215 216 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 217 CriticalPathRCs.clear(); 218 CriticalPathRCs.push_back(isPPC64() ? 219 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 220 } 221 222 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 223 unsigned NumRegionInstrs) const { 224 // The GenericScheduler that we use defaults to scheduling bottom up only. 225 // We want to schedule from both the top and the bottom and so we set 226 // OnlyBottomUp to false. 227 // We want to do bi-directional scheduling since it provides a more balanced 228 // schedule leading to better performance. 229 Policy.OnlyBottomUp = false; 230 // Spilling is generally expensive on all PPC cores, so always enable 231 // register-pressure tracking. 232 Policy.ShouldTrackPressure = true; 233 } 234 235 bool PPCSubtarget::useAA() const { 236 return true; 237 } 238 239 bool PPCSubtarget::enableSubRegLiveness() const { 240 return UseSubRegLiveness; 241 } 242 243 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { 244 // Large code model always uses the TOC even for local symbols. 245 if (TM.getCodeModel() == CodeModel::Large) 246 return true; 247 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 248 return false; 249 return true; 250 } 251 252 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 253 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 254 255 bool PPCSubtarget::isUsingPCRelativeCalls() const { 256 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() && 257 CodeModel::Medium == getTargetMachine().getCodeModel(); 258 } 259 260 // GlobalISEL 261 const CallLowering *PPCSubtarget::getCallLowering() const { 262 return CallLoweringInfo.get(); 263 } 264 265 const RegisterBankInfo *PPCSubtarget::getRegBankInfo() const { 266 return RegBankInfo.get(); 267 } 268 269 const LegalizerInfo *PPCSubtarget::getLegalizerInfo() const { 270 return Legalizer.get(); 271 } 272 273 InstructionSelector *PPCSubtarget::getInstructionSelector() const { 274 return InstSelector.get(); 275 } 276