1*0b57cec5SDimitry Andric//===-- PPCScheduleG5.td - PPC G5 Scheduling Definitions ---*- tablegen -*-===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric// 9*0b57cec5SDimitry Andric// This file defines the itinerary class data for the G5 (970) processor. 10*0b57cec5SDimitry Andric// 11*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andricdef G5_BPU : FuncUnit; // Branch unit 14*0b57cec5SDimitry Andricdef G5_SLU : FuncUnit; // Store/load unit 15*0b57cec5SDimitry Andricdef G5_SRU : FuncUnit; // special register unit 16*0b57cec5SDimitry Andricdef G5_IU1 : FuncUnit; // integer unit 1 (simple) 17*0b57cec5SDimitry Andricdef G5_IU2 : FuncUnit; // integer unit 2 (complex) 18*0b57cec5SDimitry Andricdef G5_FPU1 : FuncUnit; // floating point unit 1 19*0b57cec5SDimitry Andricdef G5_FPU2 : FuncUnit; // floating point unit 2 20*0b57cec5SDimitry Andricdef G5_VPU : FuncUnit; // vector permutation unit 21*0b57cec5SDimitry Andricdef G5_VIU1 : FuncUnit; // vector integer unit 1 (simple) 22*0b57cec5SDimitry Andricdef G5_VIU2 : FuncUnit; // vector integer unit 2 (complex) 23*0b57cec5SDimitry Andricdef G5_VFPU : FuncUnit; // vector floating point unit 24*0b57cec5SDimitry Andric 25*0b57cec5SDimitry Andricdef G5Itineraries : ProcessorItineraries< 26*0b57cec5SDimitry Andric [G5_IU1, G5_IU2, G5_SLU, G5_BPU, G5_FPU1, G5_FPU2, 27*0b57cec5SDimitry Andric G5_VFPU, G5_VIU1, G5_VIU2, G5_VPU], [], [ 28*0b57cec5SDimitry Andric InstrItinData<IIC_IntSimple , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 29*0b57cec5SDimitry Andric InstrItinData<IIC_IntGeneral , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 30*0b57cec5SDimitry Andric InstrItinData<IIC_IntCompare , [InstrStage<3, [G5_IU1, G5_IU2]>]>, 31*0b57cec5SDimitry Andric InstrItinData<IIC_IntDivD , [InstrStage<68, [G5_IU1]>]>, 32*0b57cec5SDimitry Andric InstrItinData<IIC_IntDivW , [InstrStage<36, [G5_IU1]>]>, 33*0b57cec5SDimitry Andric InstrItinData<IIC_IntMFFS , [InstrStage<6, [G5_IU2]>]>, 34*0b57cec5SDimitry Andric InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G5_VFPU]>]>, 35*0b57cec5SDimitry Andric InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, 36*0b57cec5SDimitry Andric InstrItinData<IIC_IntMulHD , [InstrStage<7, [G5_IU1, G5_IU2]>]>, 37*0b57cec5SDimitry Andric InstrItinData<IIC_IntMulHW , [InstrStage<5, [G5_IU1, G5_IU2]>]>, 38*0b57cec5SDimitry Andric InstrItinData<IIC_IntMulHWU , [InstrStage<5, [G5_IU1, G5_IU2]>]>, 39*0b57cec5SDimitry Andric InstrItinData<IIC_IntMulLI , [InstrStage<4, [G5_IU1, G5_IU2]>]>, 40*0b57cec5SDimitry Andric InstrItinData<IIC_IntRFID , [InstrStage<1, [G5_IU2]>]>, 41*0b57cec5SDimitry Andric InstrItinData<IIC_IntRotateD , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 42*0b57cec5SDimitry Andric InstrItinData<IIC_IntRotateDI , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 43*0b57cec5SDimitry Andric InstrItinData<IIC_IntRotate , [InstrStage<4, [G5_IU1, G5_IU2]>]>, 44*0b57cec5SDimitry Andric InstrItinData<IIC_IntShift , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 45*0b57cec5SDimitry Andric InstrItinData<IIC_IntTrapD , [InstrStage<1, [G5_IU1, G5_IU2]>]>, 46*0b57cec5SDimitry Andric InstrItinData<IIC_IntTrapW , [InstrStage<1, [G5_IU1, G5_IU2]>]>, 47*0b57cec5SDimitry Andric InstrItinData<IIC_BrB , [InstrStage<1, [G5_BPU]>]>, 48*0b57cec5SDimitry Andric InstrItinData<IIC_BrCR , [InstrStage<4, [G5_BPU]>]>, 49*0b57cec5SDimitry Andric InstrItinData<IIC_BrMCR , [InstrStage<2, [G5_BPU]>]>, 50*0b57cec5SDimitry Andric InstrItinData<IIC_BrMCRX , [InstrStage<3, [G5_BPU]>]>, 51*0b57cec5SDimitry Andric InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G5_SLU]>]>, 52*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLoad , [InstrStage<3, [G5_SLU]>]>, 53*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>, 54*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G5_SLU]>]>, 55*0b57cec5SDimitry Andric InstrItinData<IIC_LdStStore , [InstrStage<3, [G5_SLU]>]>, 56*0b57cec5SDimitry Andric InstrItinData<IIC_LdStDSS , [InstrStage<10, [G5_SLU]>]>, 57*0b57cec5SDimitry Andric InstrItinData<IIC_LdStICBI , [InstrStage<40, [G5_SLU]>]>, 58*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTFD , [InstrStage<4, [G5_SLU]>]>, 59*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [G5_SLU]>]>, 60*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLD , [InstrStage<3, [G5_SLU]>]>, 61*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLDU , [InstrStage<3, [G5_SLU]>]>, 62*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLDUX , [InstrStage<3, [G5_SLU]>]>, 63*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLDARX , [InstrStage<11, [G5_SLU]>]>, 64*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLFD , [InstrStage<3, [G5_SLU]>]>, 65*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLFDU , [InstrStage<5, [G5_SLU]>]>, 66*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLFDUX , [InstrStage<5, [G5_SLU]>]>, 67*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLHA , [InstrStage<5, [G5_SLU]>]>, 68*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLHAU , [InstrStage<5, [G5_SLU]>]>, 69*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLHAUX , [InstrStage<5, [G5_SLU]>]>, 70*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLMW , [InstrStage<64, [G5_SLU]>]>, 71*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G5_SLU]>]>, 72*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLWA , [InstrStage<5, [G5_SLU]>]>, 73*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLWARX , [InstrStage<11, [G5_SLU]>]>, 74*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSLBIA , [InstrStage<40, [G5_SLU]>]>, // needs work 75*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [G5_SLU]>]>, 76*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTD , [InstrStage<3, [G5_SLU]>]>, 77*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTU , [InstrStage<3, [G5_SLU]>]>, 78*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTUX , [InstrStage<3, [G5_SLU]>]>, 79*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [G5_SLU]>]>, 80*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [G5_SLU]>]>, 81*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [G5_SLU]>]>, 82*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSync , [InstrStage<35, [G5_SLU]>]>, 83*0b57cec5SDimitry Andric InstrItinData<IIC_SprISYNC , [InstrStage<40, [G5_SLU]>]>, // needs work 84*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFSR , [InstrStage<3, [G5_SLU]>]>, 85*0b57cec5SDimitry Andric InstrItinData<IIC_SprMTMSR , [InstrStage<3, [G5_SLU]>]>, 86*0b57cec5SDimitry Andric InstrItinData<IIC_SprMTSR , [InstrStage<3, [G5_SLU]>]>, 87*0b57cec5SDimitry Andric InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G5_SLU]>]>, 88*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFCR , [InstrStage<2, [G5_IU2]>]>, 89*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFCRF , [InstrStage<2, [G5_IU2]>]>, 90*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G5_IU2]>]>, 91*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G5_IU2]>]>, 92*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFTB , [InstrStage<10, [G5_IU2]>]>, 93*0b57cec5SDimitry Andric InstrItinData<IIC_SprMTSPR , [InstrStage<8, [G5_IU2]>]>, 94*0b57cec5SDimitry Andric InstrItinData<IIC_SprSC , [InstrStage<1, [G5_IU2]>]>, 95*0b57cec5SDimitry Andric InstrItinData<IIC_FPGeneral , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, 96*0b57cec5SDimitry Andric InstrItinData<IIC_FPAddSub , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, 97*0b57cec5SDimitry Andric InstrItinData<IIC_FPCompare , [InstrStage<8, [G5_FPU1, G5_FPU2]>]>, 98*0b57cec5SDimitry Andric InstrItinData<IIC_FPDivD , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>, 99*0b57cec5SDimitry Andric InstrItinData<IIC_FPDivS , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>, 100*0b57cec5SDimitry Andric InstrItinData<IIC_FPFused , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, 101*0b57cec5SDimitry Andric InstrItinData<IIC_FPRes , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, 102*0b57cec5SDimitry Andric InstrItinData<IIC_FPSqrtD , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>, 103*0b57cec5SDimitry Andric InstrItinData<IIC_FPSqrtS , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>, 104*0b57cec5SDimitry Andric InstrItinData<IIC_VecGeneral , [InstrStage<2, [G5_VIU1]>]>, 105*0b57cec5SDimitry Andric InstrItinData<IIC_VecFP , [InstrStage<8, [G5_VFPU]>]>, 106*0b57cec5SDimitry Andric InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G5_VFPU]>]>, 107*0b57cec5SDimitry Andric InstrItinData<IIC_VecComplex , [InstrStage<5, [G5_VIU2]>]>, 108*0b57cec5SDimitry Andric InstrItinData<IIC_VecPerm , [InstrStage<3, [G5_VPU]>]>, 109*0b57cec5SDimitry Andric InstrItinData<IIC_VecFPRound , [InstrStage<8, [G5_VFPU]>]>, 110*0b57cec5SDimitry Andric InstrItinData<IIC_VecVSL , [InstrStage<2, [G5_VIU1]>]>, 111*0b57cec5SDimitry Andric InstrItinData<IIC_VecVSR , [InstrStage<3, [G5_VPU]>]> 112*0b57cec5SDimitry Andric]>; 113*0b57cec5SDimitry Andric 114*0b57cec5SDimitry Andric// ===---------------------------------------------------------------------===// 115*0b57cec5SDimitry Andric// G5 machine model for scheduling and other instruction cost heuristics. 116*0b57cec5SDimitry Andric 117*0b57cec5SDimitry Andricdef G5Model : SchedMachineModel { 118*0b57cec5SDimitry Andric let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle. 119*0b57cec5SDimitry Andric let LoadLatency = 3; // Optimistic load latency assuming bypass. 120*0b57cec5SDimitry Andric // This is overriden by OperandCycles if the 121*0b57cec5SDimitry Andric // Itineraries are queried instead. 122*0b57cec5SDimitry Andric let MispredictPenalty = 16; 123*0b57cec5SDimitry Andric 124*0b57cec5SDimitry Andric let CompleteModel = 0; 125*0b57cec5SDimitry Andric 126*0b57cec5SDimitry Andric let Itineraries = G5Itineraries; 127*0b57cec5SDimitry Andric} 128*0b57cec5SDimitry Andric 129