1//===-- PPCScheduleG4.td - PPC G4 Scheduling Definitions ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the itinerary class data for the G4 (7400) processor. 10// 11//===----------------------------------------------------------------------===// 12 13def G4_BPU : FuncUnit; // Branch unit 14def G4_SLU : FuncUnit; // Store/load unit 15def G4_SRU : FuncUnit; // special register unit 16def G4_IU1 : FuncUnit; // integer unit 1 (simple) 17def G4_IU2 : FuncUnit; // integer unit 2 (complex) 18def G4_FPU1 : FuncUnit; // floating point unit 1 19def G4_VPU : FuncUnit; // vector permutation unit 20def G4_VIU1 : FuncUnit; // vector integer unit 1 (simple) 21def G4_VIU2 : FuncUnit; // vector integer unit 2 (complex) 22def G4_VFPU : FuncUnit; // vector floating point unit 23 24def G4Itineraries : ProcessorItineraries< 25 [G4_IU1, G4_IU2, G4_SLU, G4_SRU, G4_BPU, G4_FPU1, 26 G4_VIU1, G4_VIU2, G4_VPU, G4_VFPU], [], [ 27 InstrItinData<IIC_IntSimple , [InstrStage<1, [G4_IU1, G4_IU2]>]>, 28 InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4_IU1, G4_IU2]>]>, 29 InstrItinData<IIC_IntCompare , [InstrStage<1, [G4_IU1, G4_IU2]>]>, 30 InstrItinData<IIC_IntDivW , [InstrStage<19, [G4_IU1]>]>, 31 InstrItinData<IIC_IntMFFS , [InstrStage<3, [G4_FPU1]>]>, 32 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G4_VIU1]>]>, 33 InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G4_FPU1]>]>, 34 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G4_IU1]>]>, 35 InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G4_IU1]>]>, 36 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4_IU1]>]>, 37 InstrItinData<IIC_IntRotate , [InstrStage<1, [G4_IU1, G4_IU2]>]>, 38 InstrItinData<IIC_IntShift , [InstrStage<1, [G4_IU1, G4_IU2]>]>, 39 InstrItinData<IIC_IntTrapW , [InstrStage<2, [G4_IU1, G4_IU2]>]>, 40 InstrItinData<IIC_BrB , [InstrStage<1, [G4_BPU]>]>, 41 InstrItinData<IIC_BrCR , [InstrStage<1, [G4_SRU]>]>, 42 InstrItinData<IIC_BrMCR , [InstrStage<1, [G4_SRU]>]>, 43 InstrItinData<IIC_BrMCRX , [InstrStage<1, [G4_SRU]>]>, 44 InstrItinData<IIC_LdStDCBF , [InstrStage<2, [G4_SLU]>]>, 45 InstrItinData<IIC_LdStDCBI , [InstrStage<2, [G4_SLU]>]>, 46 InstrItinData<IIC_LdStLoad , [InstrStage<2, [G4_SLU]>]>, 47 InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G4_SLU]>]>, 48 InstrItinData<IIC_LdStLoadUpdX, [InstrStage<2, [G4_SLU]>]>, 49 InstrItinData<IIC_LdStStore , [InstrStage<2, [G4_SLU]>]>, 50 InstrItinData<IIC_LdStSTU , [InstrStage<2, [G4_SLU]>]>, 51 InstrItinData<IIC_LdStSTUX , [InstrStage<2, [G4_SLU]>]>, 52 InstrItinData<IIC_LdStDSS , [InstrStage<2, [G4_SLU]>]>, 53 InstrItinData<IIC_LdStICBI , [InstrStage<2, [G4_SLU]>]>, 54 InstrItinData<IIC_LdStSTFD , [InstrStage<2, [G4_SLU]>]>, 55 InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G4_SLU]>]>, 56 InstrItinData<IIC_LdStLFD , [InstrStage<2, [G4_SLU]>]>, 57 InstrItinData<IIC_LdStLFDU , [InstrStage<2, [G4_SLU]>]>, 58 InstrItinData<IIC_LdStLFDUX , [InstrStage<2, [G4_SLU]>]>, 59 InstrItinData<IIC_LdStLHA , [InstrStage<2, [G4_SLU]>]>, 60 InstrItinData<IIC_LdStLHAU , [InstrStage<2, [G4_SLU]>]>, 61 InstrItinData<IIC_LdStLHAUX , [InstrStage<2, [G4_SLU]>]>, 62 InstrItinData<IIC_LdStLMW , [InstrStage<34, [G4_SLU]>]>, 63 InstrItinData<IIC_LdStLVecX , [InstrStage<2, [G4_SLU]>]>, 64 InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G4_SLU]>]>, 65 InstrItinData<IIC_LdStSTVEBX , [InstrStage<2, [G4_SLU]>]>, 66 InstrItinData<IIC_LdStSTWCX , [InstrStage<5, [G4_SLU]>]>, 67 InstrItinData<IIC_LdStSync , [InstrStage<8, [G4_SLU]>]>, 68 InstrItinData<IIC_SprISYNC , [InstrStage<2, [G4_SRU]>]>, 69 InstrItinData<IIC_SprMFSR , [InstrStage<3, [G4_SRU]>]>, 70 InstrItinData<IIC_SprMTMSR , [InstrStage<1, [G4_SRU]>]>, 71 InstrItinData<IIC_SprMTSR , [InstrStage<2, [G4_SRU]>]>, 72 InstrItinData<IIC_SprTLBSYNC , [InstrStage<8, [G4_SRU]>]>, 73 InstrItinData<IIC_SprMFCR , [InstrStage<1, [G4_SRU]>]>, 74 InstrItinData<IIC_SprMFMSR , [InstrStage<1, [G4_SRU]>]>, 75 InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G4_SRU]>]>, 76 InstrItinData<IIC_SprMFTB , [InstrStage<1, [G4_SRU]>]>, 77 InstrItinData<IIC_SprMTSPR , [InstrStage<2, [G4_SRU]>]>, 78 InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [G4_SRU]>]>, 79 InstrItinData<IIC_SprRFI , [InstrStage<2, [G4_SRU]>]>, 80 InstrItinData<IIC_SprSC , [InstrStage<2, [G4_SRU]>]>, 81 InstrItinData<IIC_FPGeneral , [InstrStage<1, [G4_FPU1]>]>, 82 InstrItinData<IIC_FPAddSub , [InstrStage<1, [G4_FPU1]>]>, 83 InstrItinData<IIC_FPCompare , [InstrStage<1, [G4_FPU1]>]>, 84 InstrItinData<IIC_FPDivD , [InstrStage<31, [G4_FPU1]>]>, 85 InstrItinData<IIC_FPDivS , [InstrStage<17, [G4_FPU1]>]>, 86 InstrItinData<IIC_FPFused , [InstrStage<1, [G4_FPU1]>]>, 87 InstrItinData<IIC_FPRes , [InstrStage<10, [G4_FPU1]>]>, 88 InstrItinData<IIC_VecGeneral , [InstrStage<1, [G4_VIU1]>]>, 89 InstrItinData<IIC_VecFP , [InstrStage<4, [G4_VFPU]>]>, 90 InstrItinData<IIC_VecFPCompare, [InstrStage<1, [G4_VIU1]>]>, 91 InstrItinData<IIC_VecComplex , [InstrStage<3, [G4_VIU2]>]>, 92 InstrItinData<IIC_VecPerm , [InstrStage<1, [G4_VPU]>]>, 93 InstrItinData<IIC_VecFPRound , [InstrStage<4, [G4_VFPU]>]>, 94 InstrItinData<IIC_VecVSL , [InstrStage<1, [G4_VIU1]>]>, 95 InstrItinData<IIC_VecVSR , [InstrStage<1, [G4_VIU1]>]> 96]>; 97