1*0b57cec5SDimitry Andric//===-- PPCScheduleG4.td - PPC G4 Scheduling Definitions ---*- tablegen -*-===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric// 9*0b57cec5SDimitry Andric// This file defines the itinerary class data for the G4 (7400) processor. 10*0b57cec5SDimitry Andric// 11*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andricdef G4_BPU : FuncUnit; // Branch unit 14*0b57cec5SDimitry Andricdef G4_SLU : FuncUnit; // Store/load unit 15*0b57cec5SDimitry Andricdef G4_SRU : FuncUnit; // special register unit 16*0b57cec5SDimitry Andricdef G4_IU1 : FuncUnit; // integer unit 1 (simple) 17*0b57cec5SDimitry Andricdef G4_IU2 : FuncUnit; // integer unit 2 (complex) 18*0b57cec5SDimitry Andricdef G4_FPU1 : FuncUnit; // floating point unit 1 19*0b57cec5SDimitry Andricdef G4_VPU : FuncUnit; // vector permutation unit 20*0b57cec5SDimitry Andricdef G4_VIU1 : FuncUnit; // vector integer unit 1 (simple) 21*0b57cec5SDimitry Andricdef G4_VIU2 : FuncUnit; // vector integer unit 2 (complex) 22*0b57cec5SDimitry Andricdef G4_VFPU : FuncUnit; // vector floating point unit 23*0b57cec5SDimitry Andric 24*0b57cec5SDimitry Andricdef G4Itineraries : ProcessorItineraries< 25*0b57cec5SDimitry Andric [G4_IU1, G4_IU2, G4_SLU, G4_SRU, G4_BPU, G4_FPU1, 26*0b57cec5SDimitry Andric G4_VIU1, G4_VIU2, G4_VPU, G4_VFPU], [], [ 27*0b57cec5SDimitry Andric InstrItinData<IIC_IntSimple , [InstrStage<1, [G4_IU1, G4_IU2]>]>, 28*0b57cec5SDimitry Andric InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4_IU1, G4_IU2]>]>, 29*0b57cec5SDimitry Andric InstrItinData<IIC_IntCompare , [InstrStage<1, [G4_IU1, G4_IU2]>]>, 30*0b57cec5SDimitry Andric InstrItinData<IIC_IntDivW , [InstrStage<19, [G4_IU1]>]>, 31*0b57cec5SDimitry Andric InstrItinData<IIC_IntMFFS , [InstrStage<3, [G4_FPU1]>]>, 32*0b57cec5SDimitry Andric InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G4_VIU1]>]>, 33*0b57cec5SDimitry Andric InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G4_FPU1]>]>, 34*0b57cec5SDimitry Andric InstrItinData<IIC_IntMulHW , [InstrStage<5, [G4_IU1]>]>, 35*0b57cec5SDimitry Andric InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G4_IU1]>]>, 36*0b57cec5SDimitry Andric InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4_IU1]>]>, 37*0b57cec5SDimitry Andric InstrItinData<IIC_IntRotate , [InstrStage<1, [G4_IU1, G4_IU2]>]>, 38*0b57cec5SDimitry Andric InstrItinData<IIC_IntShift , [InstrStage<1, [G4_IU1, G4_IU2]>]>, 39*0b57cec5SDimitry Andric InstrItinData<IIC_IntTrapW , [InstrStage<2, [G4_IU1, G4_IU2]>]>, 40*0b57cec5SDimitry Andric InstrItinData<IIC_BrB , [InstrStage<1, [G4_BPU]>]>, 41*0b57cec5SDimitry Andric InstrItinData<IIC_BrCR , [InstrStage<1, [G4_SRU]>]>, 42*0b57cec5SDimitry Andric InstrItinData<IIC_BrMCR , [InstrStage<1, [G4_SRU]>]>, 43*0b57cec5SDimitry Andric InstrItinData<IIC_BrMCRX , [InstrStage<1, [G4_SRU]>]>, 44*0b57cec5SDimitry Andric InstrItinData<IIC_LdStDCBF , [InstrStage<2, [G4_SLU]>]>, 45*0b57cec5SDimitry Andric InstrItinData<IIC_LdStDCBI , [InstrStage<2, [G4_SLU]>]>, 46*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLoad , [InstrStage<2, [G4_SLU]>]>, 47*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G4_SLU]>]>, 48*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLoadUpdX, [InstrStage<2, [G4_SLU]>]>, 49*0b57cec5SDimitry Andric InstrItinData<IIC_LdStStore , [InstrStage<2, [G4_SLU]>]>, 50*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTU , [InstrStage<2, [G4_SLU]>]>, 51*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTUX , [InstrStage<2, [G4_SLU]>]>, 52*0b57cec5SDimitry Andric InstrItinData<IIC_LdStDSS , [InstrStage<2, [G4_SLU]>]>, 53*0b57cec5SDimitry Andric InstrItinData<IIC_LdStICBI , [InstrStage<2, [G4_SLU]>]>, 54*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTFD , [InstrStage<2, [G4_SLU]>]>, 55*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G4_SLU]>]>, 56*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLFD , [InstrStage<2, [G4_SLU]>]>, 57*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLFDU , [InstrStage<2, [G4_SLU]>]>, 58*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLFDUX , [InstrStage<2, [G4_SLU]>]>, 59*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLHA , [InstrStage<2, [G4_SLU]>]>, 60*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLHAU , [InstrStage<2, [G4_SLU]>]>, 61*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLHAUX , [InstrStage<2, [G4_SLU]>]>, 62*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLMW , [InstrStage<34, [G4_SLU]>]>, 63*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLVecX , [InstrStage<2, [G4_SLU]>]>, 64*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G4_SLU]>]>, 65*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTVEBX , [InstrStage<2, [G4_SLU]>]>, 66*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTWCX , [InstrStage<5, [G4_SLU]>]>, 67*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSync , [InstrStage<8, [G4_SLU]>]>, 68*0b57cec5SDimitry Andric InstrItinData<IIC_SprISYNC , [InstrStage<2, [G4_SRU]>]>, 69*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFSR , [InstrStage<3, [G4_SRU]>]>, 70*0b57cec5SDimitry Andric InstrItinData<IIC_SprMTMSR , [InstrStage<1, [G4_SRU]>]>, 71*0b57cec5SDimitry Andric InstrItinData<IIC_SprMTSR , [InstrStage<2, [G4_SRU]>]>, 72*0b57cec5SDimitry Andric InstrItinData<IIC_SprTLBSYNC , [InstrStage<8, [G4_SRU]>]>, 73*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFCR , [InstrStage<1, [G4_SRU]>]>, 74*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFMSR , [InstrStage<1, [G4_SRU]>]>, 75*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G4_SRU]>]>, 76*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFTB , [InstrStage<1, [G4_SRU]>]>, 77*0b57cec5SDimitry Andric InstrItinData<IIC_SprMTSPR , [InstrStage<2, [G4_SRU]>]>, 78*0b57cec5SDimitry Andric InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [G4_SRU]>]>, 79*0b57cec5SDimitry Andric InstrItinData<IIC_SprRFI , [InstrStage<2, [G4_SRU]>]>, 80*0b57cec5SDimitry Andric InstrItinData<IIC_SprSC , [InstrStage<2, [G4_SRU]>]>, 81*0b57cec5SDimitry Andric InstrItinData<IIC_FPGeneral , [InstrStage<1, [G4_FPU1]>]>, 82*0b57cec5SDimitry Andric InstrItinData<IIC_FPAddSub , [InstrStage<1, [G4_FPU1]>]>, 83*0b57cec5SDimitry Andric InstrItinData<IIC_FPCompare , [InstrStage<1, [G4_FPU1]>]>, 84*0b57cec5SDimitry Andric InstrItinData<IIC_FPDivD , [InstrStage<31, [G4_FPU1]>]>, 85*0b57cec5SDimitry Andric InstrItinData<IIC_FPDivS , [InstrStage<17, [G4_FPU1]>]>, 86*0b57cec5SDimitry Andric InstrItinData<IIC_FPFused , [InstrStage<1, [G4_FPU1]>]>, 87*0b57cec5SDimitry Andric InstrItinData<IIC_FPRes , [InstrStage<10, [G4_FPU1]>]>, 88*0b57cec5SDimitry Andric InstrItinData<IIC_VecGeneral , [InstrStage<1, [G4_VIU1]>]>, 89*0b57cec5SDimitry Andric InstrItinData<IIC_VecFP , [InstrStage<4, [G4_VFPU]>]>, 90*0b57cec5SDimitry Andric InstrItinData<IIC_VecFPCompare, [InstrStage<1, [G4_VIU1]>]>, 91*0b57cec5SDimitry Andric InstrItinData<IIC_VecComplex , [InstrStage<3, [G4_VIU2]>]>, 92*0b57cec5SDimitry Andric InstrItinData<IIC_VecPerm , [InstrStage<1, [G4_VPU]>]>, 93*0b57cec5SDimitry Andric InstrItinData<IIC_VecFPRound , [InstrStage<4, [G4_VFPU]>]>, 94*0b57cec5SDimitry Andric InstrItinData<IIC_VecVSL , [InstrStage<1, [G4_VIU1]>]>, 95*0b57cec5SDimitry Andric InstrItinData<IIC_VecVSR , [InstrStage<1, [G4_VIU1]>]> 96*0b57cec5SDimitry Andric]>; 97