1 //===--------- PPCPreEmitPeephole.cpp - Late peephole optimizations -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // A pre-emit peephole for catching opportunities introduced by late passes such 10 // as MachineBlockPlacement. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPC.h" 15 #include "PPCInstrInfo.h" 16 #include "PPCSubtarget.h" 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/Statistic.h" 19 #include "llvm/CodeGen/LivePhysRegs.h" 20 #include "llvm/CodeGen/MachineBasicBlock.h" 21 #include "llvm/CodeGen/MachineFunctionPass.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/RegisterScavenging.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/Support/CommandLine.h" 27 #include "llvm/Support/Debug.h" 28 29 using namespace llvm; 30 31 #define DEBUG_TYPE "ppc-pre-emit-peephole" 32 33 STATISTIC(NumRRConvertedInPreEmit, 34 "Number of r+r instructions converted to r+i in pre-emit peephole"); 35 STATISTIC(NumRemovedInPreEmit, 36 "Number of instructions deleted in pre-emit peephole"); 37 STATISTIC(NumberOfSelfCopies, 38 "Number of self copy instructions eliminated"); 39 STATISTIC(NumFrameOffFoldInPreEmit, 40 "Number of folding frame offset by using r+r in pre-emit peephole"); 41 42 static cl::opt<bool> 43 EnablePCRelLinkerOpt("ppc-pcrel-linker-opt", cl::Hidden, cl::init(true), 44 cl::desc("enable PC Relative linker optimization")); 45 46 static cl::opt<bool> 47 RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true), 48 cl::desc("Run pre-emit peephole optimizations.")); 49 50 static cl::opt<uint64_t> 51 DSCRValue("ppc-set-dscr", cl::Hidden, 52 cl::desc("Set the Data Stream Control Register.")); 53 54 namespace { 55 56 static bool hasPCRelativeForm(MachineInstr &Use) { 57 switch (Use.getOpcode()) { 58 default: 59 return false; 60 case PPC::LBZ: 61 case PPC::LBZ8: 62 case PPC::LHA: 63 case PPC::LHA8: 64 case PPC::LHZ: 65 case PPC::LHZ8: 66 case PPC::LWZ: 67 case PPC::LWZ8: 68 case PPC::STB: 69 case PPC::STB8: 70 case PPC::STH: 71 case PPC::STH8: 72 case PPC::STW: 73 case PPC::STW8: 74 case PPC::LD: 75 case PPC::STD: 76 case PPC::LWA: 77 case PPC::LXSD: 78 case PPC::LXSSP: 79 case PPC::LXV: 80 case PPC::STXSD: 81 case PPC::STXSSP: 82 case PPC::STXV: 83 case PPC::LFD: 84 case PPC::LFS: 85 case PPC::STFD: 86 case PPC::STFS: 87 case PPC::DFLOADf32: 88 case PPC::DFLOADf64: 89 case PPC::DFSTOREf32: 90 case PPC::DFSTOREf64: 91 return true; 92 } 93 } 94 95 class PPCPreEmitPeephole : public MachineFunctionPass { 96 public: 97 static char ID; 98 PPCPreEmitPeephole() : MachineFunctionPass(ID) { 99 initializePPCPreEmitPeepholePass(*PassRegistry::getPassRegistry()); 100 } 101 102 void getAnalysisUsage(AnalysisUsage &AU) const override { 103 MachineFunctionPass::getAnalysisUsage(AU); 104 } 105 106 MachineFunctionProperties getRequiredProperties() const override { 107 return MachineFunctionProperties().set( 108 MachineFunctionProperties::Property::NoVRegs); 109 } 110 111 // This function removes any redundant load immediates. It has two level 112 // loops - The outer loop finds the load immediates BBI that could be used 113 // to replace following redundancy. The inner loop scans instructions that 114 // after BBI to find redundancy and update kill/dead flags accordingly. If 115 // AfterBBI is the same as BBI, it is redundant, otherwise any instructions 116 // that modify the def register of BBI would break the scanning. 117 // DeadOrKillToUnset is a pointer to the previous operand that had the 118 // kill/dead flag set. It keeps track of the def register of BBI, the use 119 // registers of AfterBBIs and the def registers of AfterBBIs. 120 bool removeRedundantLIs(MachineBasicBlock &MBB, 121 const TargetRegisterInfo *TRI) { 122 LLVM_DEBUG(dbgs() << "Remove redundant load immediates from MBB:\n"; 123 MBB.dump(); dbgs() << "\n"); 124 125 DenseSet<MachineInstr *> InstrsToErase; 126 for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) { 127 // Skip load immediate that is marked to be erased later because it 128 // cannot be used to replace any other instructions. 129 if (InstrsToErase.contains(&*BBI)) 130 continue; 131 // Skip non-load immediate. 132 unsigned Opc = BBI->getOpcode(); 133 if (Opc != PPC::LI && Opc != PPC::LI8 && Opc != PPC::LIS && 134 Opc != PPC::LIS8) 135 continue; 136 // Skip load immediate, where the operand is a relocation (e.g., $r3 = 137 // LI target-flags(ppc-lo) %const.0). 138 if (!BBI->getOperand(1).isImm()) 139 continue; 140 assert(BBI->getOperand(0).isReg() && 141 "Expected a register for the first operand"); 142 143 LLVM_DEBUG(dbgs() << "Scanning after load immediate: "; BBI->dump();); 144 145 Register Reg = BBI->getOperand(0).getReg(); 146 int64_t Imm = BBI->getOperand(1).getImm(); 147 MachineOperand *DeadOrKillToUnset = nullptr; 148 if (BBI->getOperand(0).isDead()) { 149 DeadOrKillToUnset = &BBI->getOperand(0); 150 LLVM_DEBUG(dbgs() << " Kill flag of " << *DeadOrKillToUnset 151 << " from load immediate " << *BBI 152 << " is a unsetting candidate\n"); 153 } 154 // This loop scans instructions after BBI to see if there is any 155 // redundant load immediate. 156 for (auto AfterBBI = std::next(BBI); AfterBBI != MBB.instr_end(); 157 ++AfterBBI) { 158 // Track the operand that kill Reg. We would unset the kill flag of 159 // the operand if there is a following redundant load immediate. 160 int KillIdx = AfterBBI->findRegisterUseOperandIdx(Reg, true, TRI); 161 162 // We can't just clear implicit kills, so if we encounter one, stop 163 // looking further. 164 if (KillIdx != -1 && AfterBBI->getOperand(KillIdx).isImplicit()) { 165 LLVM_DEBUG(dbgs() 166 << "Encountered an implicit kill, cannot proceed: "); 167 LLVM_DEBUG(AfterBBI->dump()); 168 break; 169 } 170 171 if (KillIdx != -1) { 172 assert(!DeadOrKillToUnset && "Shouldn't kill same register twice"); 173 DeadOrKillToUnset = &AfterBBI->getOperand(KillIdx); 174 LLVM_DEBUG(dbgs() 175 << " Kill flag of " << *DeadOrKillToUnset << " from " 176 << *AfterBBI << " is a unsetting candidate\n"); 177 } 178 179 if (!AfterBBI->modifiesRegister(Reg, TRI)) 180 continue; 181 // Finish scanning because Reg is overwritten by a non-load 182 // instruction. 183 if (AfterBBI->getOpcode() != Opc) 184 break; 185 assert(AfterBBI->getOperand(0).isReg() && 186 "Expected a register for the first operand"); 187 // Finish scanning because Reg is overwritten by a relocation or a 188 // different value. 189 if (!AfterBBI->getOperand(1).isImm() || 190 AfterBBI->getOperand(1).getImm() != Imm) 191 break; 192 193 // It loads same immediate value to the same Reg, which is redundant. 194 // We would unset kill flag in previous Reg usage to extend live range 195 // of Reg first, then remove the redundancy. 196 if (DeadOrKillToUnset) { 197 LLVM_DEBUG(dbgs() 198 << " Unset dead/kill flag of " << *DeadOrKillToUnset 199 << " from " << *DeadOrKillToUnset->getParent()); 200 if (DeadOrKillToUnset->isDef()) 201 DeadOrKillToUnset->setIsDead(false); 202 else 203 DeadOrKillToUnset->setIsKill(false); 204 } 205 DeadOrKillToUnset = 206 AfterBBI->findRegisterDefOperand(Reg, true, true, TRI); 207 if (DeadOrKillToUnset) 208 LLVM_DEBUG(dbgs() 209 << " Dead flag of " << *DeadOrKillToUnset << " from " 210 << *AfterBBI << " is a unsetting candidate\n"); 211 InstrsToErase.insert(&*AfterBBI); 212 LLVM_DEBUG(dbgs() << " Remove redundant load immediate: "; 213 AfterBBI->dump()); 214 } 215 } 216 217 for (MachineInstr *MI : InstrsToErase) { 218 MI->eraseFromParent(); 219 } 220 NumRemovedInPreEmit += InstrsToErase.size(); 221 return !InstrsToErase.empty(); 222 } 223 224 // Check if this instruction is a PLDpc that is part of a GOT indirect 225 // access. 226 bool isGOTPLDpc(MachineInstr &Instr) { 227 if (Instr.getOpcode() != PPC::PLDpc) 228 return false; 229 230 // The result must be a register. 231 const MachineOperand &LoadedAddressReg = Instr.getOperand(0); 232 if (!LoadedAddressReg.isReg()) 233 return false; 234 235 // Make sure that this is a global symbol. 236 const MachineOperand &SymbolOp = Instr.getOperand(1); 237 if (!SymbolOp.isGlobal()) 238 return false; 239 240 // Finally return true only if the GOT flag is present. 241 return (SymbolOp.getTargetFlags() & PPCII::MO_GOT_FLAG); 242 } 243 244 bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) { 245 MachineFunction *MF = MBB.getParent(); 246 // If the linker opt is disabled then just return. 247 if (!EnablePCRelLinkerOpt) 248 return false; 249 250 // Add this linker opt only if we are using PC Relative memops. 251 if (!MF->getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls()) 252 return false; 253 254 // Struct to keep track of one def/use pair for a GOT indirect access. 255 struct GOTDefUsePair { 256 MachineBasicBlock::iterator DefInst; 257 MachineBasicBlock::iterator UseInst; 258 Register DefReg; 259 Register UseReg; 260 bool StillValid; 261 }; 262 // Vector of def/ues pairs in this basic block. 263 SmallVector<GOTDefUsePair, 4> CandPairs; 264 SmallVector<GOTDefUsePair, 4> ValidPairs; 265 bool MadeChange = false; 266 267 // Run through all of the instructions in the basic block and try to 268 // collect potential pairs of GOT indirect access instructions. 269 for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) { 270 // Look for the initial GOT indirect load. 271 if (isGOTPLDpc(*BBI)) { 272 GOTDefUsePair CurrentPair{BBI, MachineBasicBlock::iterator(), 273 BBI->getOperand(0).getReg(), 274 PPC::NoRegister, true}; 275 CandPairs.push_back(CurrentPair); 276 continue; 277 } 278 279 // We haven't encountered any new PLD instructions, nothing to check. 280 if (CandPairs.empty()) 281 continue; 282 283 // Run through the candidate pairs and see if any of the registers 284 // defined in the PLD instructions are used by this instruction. 285 // Note: the size of CandPairs can change in the loop. 286 for (unsigned Idx = 0; Idx < CandPairs.size(); Idx++) { 287 GOTDefUsePair &Pair = CandPairs[Idx]; 288 // The instruction does not use or modify this PLD's def reg, 289 // ignore it. 290 if (!BBI->readsRegister(Pair.DefReg, TRI) && 291 !BBI->modifiesRegister(Pair.DefReg, TRI)) 292 continue; 293 294 // The use needs to be used in the address compuation and not 295 // as the register being stored for a store. 296 const MachineOperand *UseOp = 297 hasPCRelativeForm(*BBI) ? &BBI->getOperand(2) : nullptr; 298 299 // Check for a valid use. 300 if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg && 301 UseOp->isUse() && UseOp->isKill()) { 302 Pair.UseInst = BBI; 303 Pair.UseReg = BBI->getOperand(0).getReg(); 304 ValidPairs.push_back(Pair); 305 } 306 CandPairs.erase(CandPairs.begin() + Idx); 307 } 308 } 309 310 // Go through all of the pairs and check for any more valid uses. 311 for (auto Pair = ValidPairs.begin(); Pair != ValidPairs.end(); Pair++) { 312 // We shouldn't be here if we don't have a valid pair. 313 assert(Pair->UseInst.isValid() && Pair->StillValid && 314 "Kept an invalid def/use pair for GOT PCRel opt"); 315 // We have found a potential pair. Search through the instructions 316 // between the def and the use to see if it is valid to mark this as a 317 // linker opt. 318 MachineBasicBlock::iterator BBI = Pair->DefInst; 319 ++BBI; 320 for (; BBI != Pair->UseInst; ++BBI) { 321 if (BBI->readsRegister(Pair->UseReg, TRI) || 322 BBI->modifiesRegister(Pair->UseReg, TRI)) { 323 Pair->StillValid = false; 324 break; 325 } 326 } 327 328 if (!Pair->StillValid) 329 continue; 330 331 // The load/store instruction that uses the address from the PLD will 332 // either use a register (for a store) or define a register (for the 333 // load). That register will be added as an implicit def to the PLD 334 // and as an implicit use on the second memory op. This is a precaution 335 // to prevent future passes from using that register between the two 336 // instructions. 337 MachineOperand ImplDef = 338 MachineOperand::CreateReg(Pair->UseReg, true, true); 339 MachineOperand ImplUse = 340 MachineOperand::CreateReg(Pair->UseReg, false, true); 341 Pair->DefInst->addOperand(ImplDef); 342 Pair->UseInst->addOperand(ImplUse); 343 344 // Create the symbol. 345 MCContext &Context = MF->getContext(); 346 MCSymbol *Symbol = Context.createNamedTempSymbol("pcrel"); 347 MachineOperand PCRelLabel = 348 MachineOperand::CreateMCSymbol(Symbol, PPCII::MO_PCREL_OPT_FLAG); 349 Pair->DefInst->addOperand(*MF, PCRelLabel); 350 Pair->UseInst->addOperand(*MF, PCRelLabel); 351 MadeChange |= true; 352 } 353 return MadeChange; 354 } 355 356 // This function removes redundant pairs of accumulator prime/unprime 357 // instructions. In some situations, it's possible the compiler inserts an 358 // accumulator prime instruction followed by an unprime instruction (e.g. 359 // when we store an accumulator after restoring it from a spill). If the 360 // accumulator is not used between the two, they can be removed. This 361 // function removes these redundant pairs from basic blocks. 362 // The algorithm is quite straightforward - every time we encounter a prime 363 // instruction, the primed register is added to a candidate set. Any use 364 // other than a prime removes the candidate from the set and any de-prime 365 // of a current candidate marks both the prime and de-prime for removal. 366 // This way we ensure we only remove prime/de-prime *pairs* with no 367 // intervening uses. 368 bool removeAccPrimeUnprime(MachineBasicBlock &MBB) { 369 DenseSet<MachineInstr *> InstrsToErase; 370 // Initially, none of the acc registers are candidates. 371 SmallVector<MachineInstr *, 8> Candidates( 372 PPC::UACCRCRegClass.getNumRegs(), nullptr); 373 374 for (MachineInstr &BBI : MBB.instrs()) { 375 unsigned Opc = BBI.getOpcode(); 376 // If we are visiting a xxmtacc instruction, we add it and its operand 377 // register to the candidate set. 378 if (Opc == PPC::XXMTACC) { 379 Register Acc = BBI.getOperand(0).getReg(); 380 assert(PPC::ACCRCRegClass.contains(Acc) && 381 "Unexpected register for XXMTACC"); 382 Candidates[Acc - PPC::ACC0] = &BBI; 383 } 384 // If we are visiting a xxmfacc instruction and its operand register is 385 // in the candidate set, we mark the two instructions for removal. 386 else if (Opc == PPC::XXMFACC) { 387 Register Acc = BBI.getOperand(0).getReg(); 388 assert(PPC::ACCRCRegClass.contains(Acc) && 389 "Unexpected register for XXMFACC"); 390 if (!Candidates[Acc - PPC::ACC0]) 391 continue; 392 InstrsToErase.insert(&BBI); 393 InstrsToErase.insert(Candidates[Acc - PPC::ACC0]); 394 } 395 // If we are visiting an instruction using an accumulator register 396 // as operand, we remove it from the candidate set. 397 else { 398 for (MachineOperand &Operand : BBI.operands()) { 399 if (!Operand.isReg()) 400 continue; 401 Register Reg = Operand.getReg(); 402 if (PPC::ACCRCRegClass.contains(Reg)) 403 Candidates[Reg - PPC::ACC0] = nullptr; 404 } 405 } 406 } 407 408 for (MachineInstr *MI : InstrsToErase) 409 MI->eraseFromParent(); 410 NumRemovedInPreEmit += InstrsToErase.size(); 411 return !InstrsToErase.empty(); 412 } 413 414 bool runOnMachineFunction(MachineFunction &MF) override { 415 // If the user wants to set the DSCR using command-line options, 416 // load in the specified value at the start of main. 417 if (DSCRValue.getNumOccurrences() > 0 && MF.getName().equals("main") && 418 MF.getFunction().hasExternalLinkage()) { 419 DSCRValue = (uint32_t)(DSCRValue & 0x01FFFFFF); // 25-bit DSCR mask 420 RegScavenger RS; 421 MachineBasicBlock &MBB = MF.front(); 422 // Find an unused GPR according to register liveness 423 RS.enterBasicBlock(MBB); 424 unsigned InDSCR = RS.FindUnusedReg(&PPC::GPRCRegClass); 425 if (InDSCR) { 426 const PPCInstrInfo *TII = 427 MF.getSubtarget<PPCSubtarget>().getInstrInfo(); 428 DebugLoc dl; 429 MachineBasicBlock::iterator IP = MBB.begin(); // Insert Point 430 // Copy the 32-bit DSCRValue integer into the GPR InDSCR using LIS and 431 // ORI, then move to DSCR. If the requested DSCR value is contained 432 // in a 16-bit signed number, we can emit a single `LI`, but the 433 // impact of saving one instruction in one function does not warrant 434 // any additional complexity in the logic here. 435 BuildMI(MBB, IP, dl, TII->get(PPC::LIS), InDSCR) 436 .addImm(DSCRValue >> 16); 437 BuildMI(MBB, IP, dl, TII->get(PPC::ORI), InDSCR) 438 .addReg(InDSCR) 439 .addImm(DSCRValue & 0xFFFF); 440 BuildMI(MBB, IP, dl, TII->get(PPC::MTUDSCR)) 441 .addReg(InDSCR, RegState::Kill); 442 } else 443 errs() << "Warning: Ran out of registers - Unable to set DSCR as " 444 "requested"; 445 } 446 447 if (skipFunction(MF.getFunction()) || !RunPreEmitPeephole) { 448 // Remove UNENCODED_NOP even when this pass is disabled. 449 // This needs to be done unconditionally so we don't emit zeros 450 // in the instruction stream. 451 SmallVector<MachineInstr *, 4> InstrsToErase; 452 for (MachineBasicBlock &MBB : MF) 453 for (MachineInstr &MI : MBB) 454 if (MI.getOpcode() == PPC::UNENCODED_NOP) 455 InstrsToErase.push_back(&MI); 456 for (MachineInstr *MI : InstrsToErase) 457 MI->eraseFromParent(); 458 return false; 459 } 460 bool Changed = false; 461 const PPCInstrInfo *TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo(); 462 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 463 SmallVector<MachineInstr *, 4> InstrsToErase; 464 for (MachineBasicBlock &MBB : MF) { 465 Changed |= removeRedundantLIs(MBB, TRI); 466 Changed |= addLinkerOpt(MBB, TRI); 467 Changed |= removeAccPrimeUnprime(MBB); 468 for (MachineInstr &MI : MBB) { 469 unsigned Opc = MI.getOpcode(); 470 if (Opc == PPC::UNENCODED_NOP) { 471 InstrsToErase.push_back(&MI); 472 continue; 473 } 474 // Detect self copies - these can result from running AADB. 475 if (PPCInstrInfo::isSameClassPhysRegCopy(Opc)) { 476 const MCInstrDesc &MCID = TII->get(Opc); 477 if (MCID.getNumOperands() == 3 && 478 MI.getOperand(0).getReg() == MI.getOperand(1).getReg() && 479 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) { 480 NumberOfSelfCopies++; 481 LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: "); 482 LLVM_DEBUG(MI.dump()); 483 InstrsToErase.push_back(&MI); 484 continue; 485 } 486 else if (MCID.getNumOperands() == 2 && 487 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) { 488 NumberOfSelfCopies++; 489 LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: "); 490 LLVM_DEBUG(MI.dump()); 491 InstrsToErase.push_back(&MI); 492 continue; 493 } 494 } 495 MachineInstr *DefMIToErase = nullptr; 496 if (TII->convertToImmediateForm(MI, &DefMIToErase)) { 497 Changed = true; 498 NumRRConvertedInPreEmit++; 499 LLVM_DEBUG(dbgs() << "Converted instruction to imm form: "); 500 LLVM_DEBUG(MI.dump()); 501 if (DefMIToErase) { 502 InstrsToErase.push_back(DefMIToErase); 503 } 504 } 505 if (TII->foldFrameOffset(MI)) { 506 Changed = true; 507 NumFrameOffFoldInPreEmit++; 508 LLVM_DEBUG(dbgs() << "Frame offset folding by using index form: "); 509 LLVM_DEBUG(MI.dump()); 510 } 511 } 512 513 // Eliminate conditional branch based on a constant CR bit by 514 // CRSET or CRUNSET. We eliminate the conditional branch or 515 // convert it into an unconditional branch. Also, if the CR bit 516 // is not used by other instructions, we eliminate CRSET as well. 517 auto I = MBB.getFirstInstrTerminator(); 518 if (I == MBB.instr_end()) 519 continue; 520 MachineInstr *Br = &*I; 521 if (Br->getOpcode() != PPC::BC && Br->getOpcode() != PPC::BCn) 522 continue; 523 MachineInstr *CRSetMI = nullptr; 524 Register CRBit = Br->getOperand(0).getReg(); 525 unsigned CRReg = getCRFromCRBit(CRBit); 526 bool SeenUse = false; 527 MachineBasicBlock::reverse_iterator It = Br, Er = MBB.rend(); 528 for (It++; It != Er; It++) { 529 if (It->modifiesRegister(CRBit, TRI)) { 530 if ((It->getOpcode() == PPC::CRUNSET || 531 It->getOpcode() == PPC::CRSET) && 532 It->getOperand(0).getReg() == CRBit) 533 CRSetMI = &*It; 534 break; 535 } 536 if (It->readsRegister(CRBit, TRI)) 537 SeenUse = true; 538 } 539 if (!CRSetMI) continue; 540 541 unsigned CRSetOp = CRSetMI->getOpcode(); 542 if ((Br->getOpcode() == PPC::BCn && CRSetOp == PPC::CRSET) || 543 (Br->getOpcode() == PPC::BC && CRSetOp == PPC::CRUNSET)) { 544 // Remove this branch since it cannot be taken. 545 InstrsToErase.push_back(Br); 546 MBB.removeSuccessor(Br->getOperand(1).getMBB()); 547 } 548 else { 549 // This conditional branch is always taken. So, remove all branches 550 // and insert an unconditional branch to the destination of this. 551 MachineBasicBlock::iterator It = Br, Er = MBB.end(); 552 for (; It != Er; It++) { 553 if (It->isDebugInstr()) continue; 554 assert(It->isTerminator() && "Non-terminator after a terminator"); 555 InstrsToErase.push_back(&*It); 556 } 557 if (!MBB.isLayoutSuccessor(Br->getOperand(1).getMBB())) { 558 ArrayRef<MachineOperand> NoCond; 559 TII->insertBranch(MBB, Br->getOperand(1).getMBB(), nullptr, 560 NoCond, Br->getDebugLoc()); 561 } 562 for (auto &Succ : MBB.successors()) 563 if (Succ != Br->getOperand(1).getMBB()) { 564 MBB.removeSuccessor(Succ); 565 break; 566 } 567 } 568 569 // If the CRBit is not used by another instruction, we can eliminate 570 // CRSET/CRUNSET instruction. 571 if (!SeenUse) { 572 // We need to check use of the CRBit in successors. 573 for (auto &SuccMBB : MBB.successors()) 574 if (SuccMBB->isLiveIn(CRBit) || SuccMBB->isLiveIn(CRReg)) { 575 SeenUse = true; 576 break; 577 } 578 if (!SeenUse) 579 InstrsToErase.push_back(CRSetMI); 580 } 581 } 582 for (MachineInstr *MI : InstrsToErase) { 583 LLVM_DEBUG(dbgs() << "PPC pre-emit peephole: erasing instruction: "); 584 LLVM_DEBUG(MI->dump()); 585 MI->eraseFromParent(); 586 NumRemovedInPreEmit++; 587 } 588 return Changed; 589 } 590 }; 591 } 592 593 INITIALIZE_PASS(PPCPreEmitPeephole, DEBUG_TYPE, "PowerPC Pre-Emit Peephole", 594 false, false) 595 char PPCPreEmitPeephole::ID = 0; 596 597 FunctionPass *llvm::createPPCPreEmitPeepholePass() { 598 return new PPCPreEmitPeephole(); 599 } 600