1 //===--------- PPCPreEmitPeephole.cpp - Late peephole optimizations -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // A pre-emit peephole for catching opportunities introduced by late passes such 10 // as MachineBlockPlacement. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPC.h" 15 #include "PPCInstrInfo.h" 16 #include "PPCSubtarget.h" 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/Statistic.h" 19 #include "llvm/CodeGen/LivePhysRegs.h" 20 #include "llvm/CodeGen/MachineBasicBlock.h" 21 #include "llvm/CodeGen/MachineFunctionPass.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/Support/CommandLine.h" 25 #include "llvm/ADT/Statistic.h" 26 #include "llvm/Support/Debug.h" 27 28 using namespace llvm; 29 30 #define DEBUG_TYPE "ppc-pre-emit-peephole" 31 32 STATISTIC(NumRRConvertedInPreEmit, 33 "Number of r+r instructions converted to r+i in pre-emit peephole"); 34 STATISTIC(NumRemovedInPreEmit, 35 "Number of instructions deleted in pre-emit peephole"); 36 STATISTIC(NumberOfSelfCopies, 37 "Number of self copy instructions eliminated"); 38 39 static cl::opt<bool> 40 RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true), 41 cl::desc("Run pre-emit peephole optimizations.")); 42 43 namespace { 44 class PPCPreEmitPeephole : public MachineFunctionPass { 45 public: 46 static char ID; 47 PPCPreEmitPeephole() : MachineFunctionPass(ID) { 48 initializePPCPreEmitPeepholePass(*PassRegistry::getPassRegistry()); 49 } 50 51 void getAnalysisUsage(AnalysisUsage &AU) const override { 52 MachineFunctionPass::getAnalysisUsage(AU); 53 } 54 55 MachineFunctionProperties getRequiredProperties() const override { 56 return MachineFunctionProperties().set( 57 MachineFunctionProperties::Property::NoVRegs); 58 } 59 60 // This function removes any redundant load immediates. It has two level 61 // loops - The outer loop finds the load immediates BBI that could be used 62 // to replace following redundancy. The inner loop scans instructions that 63 // after BBI to find redundancy and update kill/dead flags accordingly. If 64 // AfterBBI is the same as BBI, it is redundant, otherwise any instructions 65 // that modify the def register of BBI would break the scanning. 66 // DeadOrKillToUnset is a pointer to the previous operand that had the 67 // kill/dead flag set. It keeps track of the def register of BBI, the use 68 // registers of AfterBBIs and the def registers of AfterBBIs. 69 bool removeRedundantLIs(MachineBasicBlock &MBB, 70 const TargetRegisterInfo *TRI) { 71 LLVM_DEBUG(dbgs() << "Remove redundant load immediates from MBB:\n"; 72 MBB.dump(); dbgs() << "\n"); 73 74 DenseSet<MachineInstr *> InstrsToErase; 75 for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) { 76 // Skip load immediate that is marked to be erased later because it 77 // cannot be used to replace any other instructions. 78 if (InstrsToErase.find(&*BBI) != InstrsToErase.end()) 79 continue; 80 // Skip non-load immediate. 81 unsigned Opc = BBI->getOpcode(); 82 if (Opc != PPC::LI && Opc != PPC::LI8 && Opc != PPC::LIS && 83 Opc != PPC::LIS8) 84 continue; 85 // Skip load immediate, where the operand is a relocation (e.g., $r3 = 86 // LI target-flags(ppc-lo) %const.0). 87 if (!BBI->getOperand(1).isImm()) 88 continue; 89 assert(BBI->getOperand(0).isReg() && 90 "Expected a register for the first operand"); 91 92 LLVM_DEBUG(dbgs() << "Scanning after load immediate: "; BBI->dump();); 93 94 Register Reg = BBI->getOperand(0).getReg(); 95 int64_t Imm = BBI->getOperand(1).getImm(); 96 MachineOperand *DeadOrKillToUnset = nullptr; 97 if (BBI->getOperand(0).isDead()) { 98 DeadOrKillToUnset = &BBI->getOperand(0); 99 LLVM_DEBUG(dbgs() << " Kill flag of " << *DeadOrKillToUnset 100 << " from load immediate " << *BBI 101 << " is a unsetting candidate\n"); 102 } 103 // This loop scans instructions after BBI to see if there is any 104 // redundant load immediate. 105 for (auto AfterBBI = std::next(BBI); AfterBBI != MBB.instr_end(); 106 ++AfterBBI) { 107 // Track the operand that kill Reg. We would unset the kill flag of 108 // the operand if there is a following redundant load immediate. 109 int KillIdx = AfterBBI->findRegisterUseOperandIdx(Reg, true, TRI); 110 if (KillIdx != -1) { 111 assert(!DeadOrKillToUnset && "Shouldn't kill same register twice"); 112 DeadOrKillToUnset = &AfterBBI->getOperand(KillIdx); 113 LLVM_DEBUG(dbgs() 114 << " Kill flag of " << *DeadOrKillToUnset << " from " 115 << *AfterBBI << " is a unsetting candidate\n"); 116 } 117 118 if (!AfterBBI->modifiesRegister(Reg, TRI)) 119 continue; 120 // Finish scanning because Reg is overwritten by a non-load 121 // instruction. 122 if (AfterBBI->getOpcode() != Opc) 123 break; 124 assert(AfterBBI->getOperand(0).isReg() && 125 "Expected a register for the first operand"); 126 // Finish scanning because Reg is overwritten by a relocation or a 127 // different value. 128 if (!AfterBBI->getOperand(1).isImm() || 129 AfterBBI->getOperand(1).getImm() != Imm) 130 break; 131 132 // It loads same immediate value to the same Reg, which is redundant. 133 // We would unset kill flag in previous Reg usage to extend live range 134 // of Reg first, then remove the redundancy. 135 if (DeadOrKillToUnset) { 136 LLVM_DEBUG(dbgs() 137 << " Unset dead/kill flag of " << *DeadOrKillToUnset 138 << " from " << *DeadOrKillToUnset->getParent()); 139 if (DeadOrKillToUnset->isDef()) 140 DeadOrKillToUnset->setIsDead(false); 141 else 142 DeadOrKillToUnset->setIsKill(false); 143 } 144 DeadOrKillToUnset = 145 AfterBBI->findRegisterDefOperand(Reg, true, true, TRI); 146 if (DeadOrKillToUnset) 147 LLVM_DEBUG(dbgs() 148 << " Dead flag of " << *DeadOrKillToUnset << " from " 149 << *AfterBBI << " is a unsetting candidate\n"); 150 InstrsToErase.insert(&*AfterBBI); 151 LLVM_DEBUG(dbgs() << " Remove redundant load immediate: "; 152 AfterBBI->dump()); 153 } 154 } 155 156 for (MachineInstr *MI : InstrsToErase) { 157 MI->eraseFromParent(); 158 } 159 NumRemovedInPreEmit += InstrsToErase.size(); 160 return !InstrsToErase.empty(); 161 } 162 163 bool runOnMachineFunction(MachineFunction &MF) override { 164 if (skipFunction(MF.getFunction()) || !RunPreEmitPeephole) 165 return false; 166 bool Changed = false; 167 const PPCInstrInfo *TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo(); 168 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 169 SmallVector<MachineInstr *, 4> InstrsToErase; 170 for (MachineBasicBlock &MBB : MF) { 171 Changed |= removeRedundantLIs(MBB, TRI); 172 for (MachineInstr &MI : MBB) { 173 unsigned Opc = MI.getOpcode(); 174 // Detect self copies - these can result from running AADB. 175 if (PPCInstrInfo::isSameClassPhysRegCopy(Opc)) { 176 const MCInstrDesc &MCID = TII->get(Opc); 177 if (MCID.getNumOperands() == 3 && 178 MI.getOperand(0).getReg() == MI.getOperand(1).getReg() && 179 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) { 180 NumberOfSelfCopies++; 181 LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: "); 182 LLVM_DEBUG(MI.dump()); 183 InstrsToErase.push_back(&MI); 184 continue; 185 } 186 else if (MCID.getNumOperands() == 2 && 187 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) { 188 NumberOfSelfCopies++; 189 LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: "); 190 LLVM_DEBUG(MI.dump()); 191 InstrsToErase.push_back(&MI); 192 continue; 193 } 194 } 195 MachineInstr *DefMIToErase = nullptr; 196 if (TII->convertToImmediateForm(MI, &DefMIToErase)) { 197 Changed = true; 198 NumRRConvertedInPreEmit++; 199 LLVM_DEBUG(dbgs() << "Converted instruction to imm form: "); 200 LLVM_DEBUG(MI.dump()); 201 if (DefMIToErase) { 202 InstrsToErase.push_back(DefMIToErase); 203 } 204 } 205 } 206 207 // Eliminate conditional branch based on a constant CR bit by 208 // CRSET or CRUNSET. We eliminate the conditional branch or 209 // convert it into an unconditional branch. Also, if the CR bit 210 // is not used by other instructions, we eliminate CRSET as well. 211 auto I = MBB.getFirstInstrTerminator(); 212 if (I == MBB.instr_end()) 213 continue; 214 MachineInstr *Br = &*I; 215 if (Br->getOpcode() != PPC::BC && Br->getOpcode() != PPC::BCn) 216 continue; 217 MachineInstr *CRSetMI = nullptr; 218 Register CRBit = Br->getOperand(0).getReg(); 219 unsigned CRReg = getCRFromCRBit(CRBit); 220 bool SeenUse = false; 221 MachineBasicBlock::reverse_iterator It = Br, Er = MBB.rend(); 222 for (It++; It != Er; It++) { 223 if (It->modifiesRegister(CRBit, TRI)) { 224 if ((It->getOpcode() == PPC::CRUNSET || 225 It->getOpcode() == PPC::CRSET) && 226 It->getOperand(0).getReg() == CRBit) 227 CRSetMI = &*It; 228 break; 229 } 230 if (It->readsRegister(CRBit, TRI)) 231 SeenUse = true; 232 } 233 if (!CRSetMI) continue; 234 235 unsigned CRSetOp = CRSetMI->getOpcode(); 236 if ((Br->getOpcode() == PPC::BCn && CRSetOp == PPC::CRSET) || 237 (Br->getOpcode() == PPC::BC && CRSetOp == PPC::CRUNSET)) { 238 // Remove this branch since it cannot be taken. 239 InstrsToErase.push_back(Br); 240 MBB.removeSuccessor(Br->getOperand(1).getMBB()); 241 } 242 else { 243 // This conditional branch is always taken. So, remove all branches 244 // and insert an unconditional branch to the destination of this. 245 MachineBasicBlock::iterator It = Br, Er = MBB.end(); 246 for (; It != Er; It++) { 247 if (It->isDebugInstr()) continue; 248 assert(It->isTerminator() && "Non-terminator after a terminator"); 249 InstrsToErase.push_back(&*It); 250 } 251 if (!MBB.isLayoutSuccessor(Br->getOperand(1).getMBB())) { 252 ArrayRef<MachineOperand> NoCond; 253 TII->insertBranch(MBB, Br->getOperand(1).getMBB(), nullptr, 254 NoCond, Br->getDebugLoc()); 255 } 256 for (auto &Succ : MBB.successors()) 257 if (Succ != Br->getOperand(1).getMBB()) { 258 MBB.removeSuccessor(Succ); 259 break; 260 } 261 } 262 263 // If the CRBit is not used by another instruction, we can eliminate 264 // CRSET/CRUNSET instruction. 265 if (!SeenUse) { 266 // We need to check use of the CRBit in successors. 267 for (auto &SuccMBB : MBB.successors()) 268 if (SuccMBB->isLiveIn(CRBit) || SuccMBB->isLiveIn(CRReg)) { 269 SeenUse = true; 270 break; 271 } 272 if (!SeenUse) 273 InstrsToErase.push_back(CRSetMI); 274 } 275 } 276 for (MachineInstr *MI : InstrsToErase) { 277 LLVM_DEBUG(dbgs() << "PPC pre-emit peephole: erasing instruction: "); 278 LLVM_DEBUG(MI->dump()); 279 MI->eraseFromParent(); 280 NumRemovedInPreEmit++; 281 } 282 return Changed; 283 } 284 }; 285 } 286 287 INITIALIZE_PASS(PPCPreEmitPeephole, DEBUG_TYPE, "PowerPC Pre-Emit Peephole", 288 false, false) 289 char PPCPreEmitPeephole::ID = 0; 290 291 FunctionPass *llvm::createPPCPreEmitPeepholePass() { 292 return new PPCPreEmitPeephole(); 293 } 294