1 //===--------- PPCPreEmitPeephole.cpp - Late peephole optimizations -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // A pre-emit peephole for catching opportunities introduced by late passes such 10 // as MachineBlockPlacement. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPC.h" 15 #include "PPCInstrInfo.h" 16 #include "PPCSubtarget.h" 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/Statistic.h" 19 #include "llvm/CodeGen/LivePhysRegs.h" 20 #include "llvm/CodeGen/MachineBasicBlock.h" 21 #include "llvm/CodeGen/MachineFunctionPass.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/RegisterScavenging.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/Support/CommandLine.h" 27 #include "llvm/Support/Debug.h" 28 29 using namespace llvm; 30 31 #define DEBUG_TYPE "ppc-pre-emit-peephole" 32 33 STATISTIC(NumRRConvertedInPreEmit, 34 "Number of r+r instructions converted to r+i in pre-emit peephole"); 35 STATISTIC(NumRemovedInPreEmit, 36 "Number of instructions deleted in pre-emit peephole"); 37 STATISTIC(NumberOfSelfCopies, 38 "Number of self copy instructions eliminated"); 39 STATISTIC(NumFrameOffFoldInPreEmit, 40 "Number of folding frame offset by using r+r in pre-emit peephole"); 41 STATISTIC(NumCmpsInPreEmit, 42 "Number of compares eliminated in pre-emit peephole"); 43 44 static cl::opt<bool> 45 EnablePCRelLinkerOpt("ppc-pcrel-linker-opt", cl::Hidden, cl::init(true), 46 cl::desc("enable PC Relative linker optimization")); 47 48 static cl::opt<bool> 49 RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true), 50 cl::desc("Run pre-emit peephole optimizations.")); 51 52 static cl::opt<uint64_t> 53 DSCRValue("ppc-set-dscr", cl::Hidden, 54 cl::desc("Set the Data Stream Control Register.")); 55 56 namespace { 57 58 static bool hasPCRelativeForm(MachineInstr &Use) { 59 switch (Use.getOpcode()) { 60 default: 61 return false; 62 case PPC::LBZ: 63 case PPC::LBZ8: 64 case PPC::LHA: 65 case PPC::LHA8: 66 case PPC::LHZ: 67 case PPC::LHZ8: 68 case PPC::LWZ: 69 case PPC::LWZ8: 70 case PPC::STB: 71 case PPC::STB8: 72 case PPC::STH: 73 case PPC::STH8: 74 case PPC::STW: 75 case PPC::STW8: 76 case PPC::LD: 77 case PPC::STD: 78 case PPC::LWA: 79 case PPC::LXSD: 80 case PPC::LXSSP: 81 case PPC::LXV: 82 case PPC::STXSD: 83 case PPC::STXSSP: 84 case PPC::STXV: 85 case PPC::LFD: 86 case PPC::LFS: 87 case PPC::STFD: 88 case PPC::STFS: 89 case PPC::DFLOADf32: 90 case PPC::DFLOADf64: 91 case PPC::DFSTOREf32: 92 case PPC::DFSTOREf64: 93 return true; 94 } 95 } 96 97 class PPCPreEmitPeephole : public MachineFunctionPass { 98 public: 99 static char ID; 100 PPCPreEmitPeephole() : MachineFunctionPass(ID) { 101 initializePPCPreEmitPeepholePass(*PassRegistry::getPassRegistry()); 102 } 103 104 void getAnalysisUsage(AnalysisUsage &AU) const override { 105 MachineFunctionPass::getAnalysisUsage(AU); 106 } 107 108 MachineFunctionProperties getRequiredProperties() const override { 109 return MachineFunctionProperties().set( 110 MachineFunctionProperties::Property::NoVRegs); 111 } 112 113 // This function removes any redundant load immediates. It has two level 114 // loops - The outer loop finds the load immediates BBI that could be used 115 // to replace following redundancy. The inner loop scans instructions that 116 // after BBI to find redundancy and update kill/dead flags accordingly. If 117 // AfterBBI is the same as BBI, it is redundant, otherwise any instructions 118 // that modify the def register of BBI would break the scanning. 119 // DeadOrKillToUnset is a pointer to the previous operand that had the 120 // kill/dead flag set. It keeps track of the def register of BBI, the use 121 // registers of AfterBBIs and the def registers of AfterBBIs. 122 bool removeRedundantLIs(MachineBasicBlock &MBB, 123 const TargetRegisterInfo *TRI) { 124 LLVM_DEBUG(dbgs() << "Remove redundant load immediates from MBB:\n"; 125 MBB.dump(); dbgs() << "\n"); 126 127 DenseSet<MachineInstr *> InstrsToErase; 128 for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) { 129 // Skip load immediate that is marked to be erased later because it 130 // cannot be used to replace any other instructions. 131 if (InstrsToErase.contains(&*BBI)) 132 continue; 133 // Skip non-load immediate. 134 unsigned Opc = BBI->getOpcode(); 135 if (Opc != PPC::LI && Opc != PPC::LI8 && Opc != PPC::LIS && 136 Opc != PPC::LIS8) 137 continue; 138 // Skip load immediate, where the operand is a relocation (e.g., $r3 = 139 // LI target-flags(ppc-lo) %const.0). 140 if (!BBI->getOperand(1).isImm()) 141 continue; 142 assert(BBI->getOperand(0).isReg() && 143 "Expected a register for the first operand"); 144 145 LLVM_DEBUG(dbgs() << "Scanning after load immediate: "; BBI->dump();); 146 147 Register Reg = BBI->getOperand(0).getReg(); 148 int64_t Imm = BBI->getOperand(1).getImm(); 149 MachineOperand *DeadOrKillToUnset = nullptr; 150 if (BBI->getOperand(0).isDead()) { 151 DeadOrKillToUnset = &BBI->getOperand(0); 152 LLVM_DEBUG(dbgs() << " Kill flag of " << *DeadOrKillToUnset 153 << " from load immediate " << *BBI 154 << " is a unsetting candidate\n"); 155 } 156 // This loop scans instructions after BBI to see if there is any 157 // redundant load immediate. 158 for (auto AfterBBI = std::next(BBI); AfterBBI != MBB.instr_end(); 159 ++AfterBBI) { 160 // Track the operand that kill Reg. We would unset the kill flag of 161 // the operand if there is a following redundant load immediate. 162 int KillIdx = AfterBBI->findRegisterUseOperandIdx(Reg, true, TRI); 163 164 // We can't just clear implicit kills, so if we encounter one, stop 165 // looking further. 166 if (KillIdx != -1 && AfterBBI->getOperand(KillIdx).isImplicit()) { 167 LLVM_DEBUG(dbgs() 168 << "Encountered an implicit kill, cannot proceed: "); 169 LLVM_DEBUG(AfterBBI->dump()); 170 break; 171 } 172 173 if (KillIdx != -1) { 174 assert(!DeadOrKillToUnset && "Shouldn't kill same register twice"); 175 DeadOrKillToUnset = &AfterBBI->getOperand(KillIdx); 176 LLVM_DEBUG(dbgs() 177 << " Kill flag of " << *DeadOrKillToUnset << " from " 178 << *AfterBBI << " is a unsetting candidate\n"); 179 } 180 181 if (!AfterBBI->modifiesRegister(Reg, TRI)) 182 continue; 183 // Finish scanning because Reg is overwritten by a non-load 184 // instruction. 185 if (AfterBBI->getOpcode() != Opc) 186 break; 187 assert(AfterBBI->getOperand(0).isReg() && 188 "Expected a register for the first operand"); 189 // Finish scanning because Reg is overwritten by a relocation or a 190 // different value. 191 if (!AfterBBI->getOperand(1).isImm() || 192 AfterBBI->getOperand(1).getImm() != Imm) 193 break; 194 195 // It loads same immediate value to the same Reg, which is redundant. 196 // We would unset kill flag in previous Reg usage to extend live range 197 // of Reg first, then remove the redundancy. 198 if (DeadOrKillToUnset) { 199 LLVM_DEBUG(dbgs() 200 << " Unset dead/kill flag of " << *DeadOrKillToUnset 201 << " from " << *DeadOrKillToUnset->getParent()); 202 if (DeadOrKillToUnset->isDef()) 203 DeadOrKillToUnset->setIsDead(false); 204 else 205 DeadOrKillToUnset->setIsKill(false); 206 } 207 DeadOrKillToUnset = 208 AfterBBI->findRegisterDefOperand(Reg, true, true, TRI); 209 if (DeadOrKillToUnset) 210 LLVM_DEBUG(dbgs() 211 << " Dead flag of " << *DeadOrKillToUnset << " from " 212 << *AfterBBI << " is a unsetting candidate\n"); 213 InstrsToErase.insert(&*AfterBBI); 214 LLVM_DEBUG(dbgs() << " Remove redundant load immediate: "; 215 AfterBBI->dump()); 216 } 217 } 218 219 for (MachineInstr *MI : InstrsToErase) { 220 MI->eraseFromParent(); 221 } 222 NumRemovedInPreEmit += InstrsToErase.size(); 223 return !InstrsToErase.empty(); 224 } 225 226 // Check if this instruction is a PLDpc that is part of a GOT indirect 227 // access. 228 bool isGOTPLDpc(MachineInstr &Instr) { 229 if (Instr.getOpcode() != PPC::PLDpc) 230 return false; 231 232 // The result must be a register. 233 const MachineOperand &LoadedAddressReg = Instr.getOperand(0); 234 if (!LoadedAddressReg.isReg()) 235 return false; 236 237 // Make sure that this is a global symbol. 238 const MachineOperand &SymbolOp = Instr.getOperand(1); 239 if (!SymbolOp.isGlobal()) 240 return false; 241 242 // Finally return true only if the GOT flag is present. 243 return (SymbolOp.getTargetFlags() & PPCII::MO_GOT_FLAG); 244 } 245 246 bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) { 247 MachineFunction *MF = MBB.getParent(); 248 // If the linker opt is disabled then just return. 249 if (!EnablePCRelLinkerOpt) 250 return false; 251 252 // Add this linker opt only if we are using PC Relative memops. 253 if (!MF->getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls()) 254 return false; 255 256 // Struct to keep track of one def/use pair for a GOT indirect access. 257 struct GOTDefUsePair { 258 MachineBasicBlock::iterator DefInst; 259 MachineBasicBlock::iterator UseInst; 260 Register DefReg; 261 Register UseReg; 262 bool StillValid; 263 }; 264 // Vector of def/ues pairs in this basic block. 265 SmallVector<GOTDefUsePair, 4> CandPairs; 266 SmallVector<GOTDefUsePair, 4> ValidPairs; 267 bool MadeChange = false; 268 269 // Run through all of the instructions in the basic block and try to 270 // collect potential pairs of GOT indirect access instructions. 271 for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) { 272 // Look for the initial GOT indirect load. 273 if (isGOTPLDpc(*BBI)) { 274 GOTDefUsePair CurrentPair{BBI, MachineBasicBlock::iterator(), 275 BBI->getOperand(0).getReg(), 276 PPC::NoRegister, true}; 277 CandPairs.push_back(CurrentPair); 278 continue; 279 } 280 281 // We haven't encountered any new PLD instructions, nothing to check. 282 if (CandPairs.empty()) 283 continue; 284 285 // Run through the candidate pairs and see if any of the registers 286 // defined in the PLD instructions are used by this instruction. 287 // Note: the size of CandPairs can change in the loop. 288 for (unsigned Idx = 0; Idx < CandPairs.size(); Idx++) { 289 GOTDefUsePair &Pair = CandPairs[Idx]; 290 // The instruction does not use or modify this PLD's def reg, 291 // ignore it. 292 if (!BBI->readsRegister(Pair.DefReg, TRI) && 293 !BBI->modifiesRegister(Pair.DefReg, TRI)) 294 continue; 295 296 // The use needs to be used in the address computation and not 297 // as the register being stored for a store. 298 const MachineOperand *UseOp = 299 hasPCRelativeForm(*BBI) ? &BBI->getOperand(2) : nullptr; 300 301 // Check for a valid use. 302 if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg && 303 UseOp->isUse() && UseOp->isKill()) { 304 Pair.UseInst = BBI; 305 Pair.UseReg = BBI->getOperand(0).getReg(); 306 ValidPairs.push_back(Pair); 307 } 308 CandPairs.erase(CandPairs.begin() + Idx); 309 } 310 } 311 312 // Go through all of the pairs and check for any more valid uses. 313 for (auto Pair = ValidPairs.begin(); Pair != ValidPairs.end(); Pair++) { 314 // We shouldn't be here if we don't have a valid pair. 315 assert(Pair->UseInst.isValid() && Pair->StillValid && 316 "Kept an invalid def/use pair for GOT PCRel opt"); 317 // We have found a potential pair. Search through the instructions 318 // between the def and the use to see if it is valid to mark this as a 319 // linker opt. 320 MachineBasicBlock::iterator BBI = Pair->DefInst; 321 ++BBI; 322 for (; BBI != Pair->UseInst; ++BBI) { 323 if (BBI->readsRegister(Pair->UseReg, TRI) || 324 BBI->modifiesRegister(Pair->UseReg, TRI)) { 325 Pair->StillValid = false; 326 break; 327 } 328 } 329 330 if (!Pair->StillValid) 331 continue; 332 333 // The load/store instruction that uses the address from the PLD will 334 // either use a register (for a store) or define a register (for the 335 // load). That register will be added as an implicit def to the PLD 336 // and as an implicit use on the second memory op. This is a precaution 337 // to prevent future passes from using that register between the two 338 // instructions. 339 MachineOperand ImplDef = 340 MachineOperand::CreateReg(Pair->UseReg, true, true); 341 MachineOperand ImplUse = 342 MachineOperand::CreateReg(Pair->UseReg, false, true); 343 Pair->DefInst->addOperand(ImplDef); 344 Pair->UseInst->addOperand(ImplUse); 345 346 // Create the symbol. 347 MCContext &Context = MF->getContext(); 348 MCSymbol *Symbol = Context.createNamedTempSymbol("pcrel"); 349 MachineOperand PCRelLabel = 350 MachineOperand::CreateMCSymbol(Symbol, PPCII::MO_PCREL_OPT_FLAG); 351 Pair->DefInst->addOperand(*MF, PCRelLabel); 352 Pair->UseInst->addOperand(*MF, PCRelLabel); 353 MadeChange |= true; 354 } 355 return MadeChange; 356 } 357 358 // This function removes redundant pairs of accumulator prime/unprime 359 // instructions. In some situations, it's possible the compiler inserts an 360 // accumulator prime instruction followed by an unprime instruction (e.g. 361 // when we store an accumulator after restoring it from a spill). If the 362 // accumulator is not used between the two, they can be removed. This 363 // function removes these redundant pairs from basic blocks. 364 // The algorithm is quite straightforward - every time we encounter a prime 365 // instruction, the primed register is added to a candidate set. Any use 366 // other than a prime removes the candidate from the set and any de-prime 367 // of a current candidate marks both the prime and de-prime for removal. 368 // This way we ensure we only remove prime/de-prime *pairs* with no 369 // intervening uses. 370 bool removeAccPrimeUnprime(MachineBasicBlock &MBB) { 371 DenseSet<MachineInstr *> InstrsToErase; 372 // Initially, none of the acc registers are candidates. 373 SmallVector<MachineInstr *, 8> Candidates( 374 PPC::UACCRCRegClass.getNumRegs(), nullptr); 375 376 for (MachineInstr &BBI : MBB.instrs()) { 377 unsigned Opc = BBI.getOpcode(); 378 // If we are visiting a xxmtacc instruction, we add it and its operand 379 // register to the candidate set. 380 if (Opc == PPC::XXMTACC) { 381 Register Acc = BBI.getOperand(0).getReg(); 382 assert(PPC::ACCRCRegClass.contains(Acc) && 383 "Unexpected register for XXMTACC"); 384 Candidates[Acc - PPC::ACC0] = &BBI; 385 } 386 // If we are visiting a xxmfacc instruction and its operand register is 387 // in the candidate set, we mark the two instructions for removal. 388 else if (Opc == PPC::XXMFACC) { 389 Register Acc = BBI.getOperand(0).getReg(); 390 assert(PPC::ACCRCRegClass.contains(Acc) && 391 "Unexpected register for XXMFACC"); 392 if (!Candidates[Acc - PPC::ACC0]) 393 continue; 394 InstrsToErase.insert(&BBI); 395 InstrsToErase.insert(Candidates[Acc - PPC::ACC0]); 396 } 397 // If we are visiting an instruction using an accumulator register 398 // as operand, we remove it from the candidate set. 399 else { 400 for (MachineOperand &Operand : BBI.operands()) { 401 if (!Operand.isReg()) 402 continue; 403 Register Reg = Operand.getReg(); 404 if (PPC::ACCRCRegClass.contains(Reg)) 405 Candidates[Reg - PPC::ACC0] = nullptr; 406 } 407 } 408 } 409 410 for (MachineInstr *MI : InstrsToErase) 411 MI->eraseFromParent(); 412 NumRemovedInPreEmit += InstrsToErase.size(); 413 return !InstrsToErase.empty(); 414 } 415 416 bool runOnMachineFunction(MachineFunction &MF) override { 417 // If the user wants to set the DSCR using command-line options, 418 // load in the specified value at the start of main. 419 if (DSCRValue.getNumOccurrences() > 0 && MF.getName().equals("main") && 420 MF.getFunction().hasExternalLinkage()) { 421 DSCRValue = (uint32_t)(DSCRValue & 0x01FFFFFF); // 25-bit DSCR mask 422 RegScavenger RS; 423 MachineBasicBlock &MBB = MF.front(); 424 // Find an unused GPR according to register liveness 425 RS.enterBasicBlock(MBB); 426 unsigned InDSCR = RS.FindUnusedReg(&PPC::GPRCRegClass); 427 if (InDSCR) { 428 const PPCInstrInfo *TII = 429 MF.getSubtarget<PPCSubtarget>().getInstrInfo(); 430 DebugLoc dl; 431 MachineBasicBlock::iterator IP = MBB.begin(); // Insert Point 432 // Copy the 32-bit DSCRValue integer into the GPR InDSCR using LIS and 433 // ORI, then move to DSCR. If the requested DSCR value is contained 434 // in a 16-bit signed number, we can emit a single `LI`, but the 435 // impact of saving one instruction in one function does not warrant 436 // any additional complexity in the logic here. 437 BuildMI(MBB, IP, dl, TII->get(PPC::LIS), InDSCR) 438 .addImm(DSCRValue >> 16); 439 BuildMI(MBB, IP, dl, TII->get(PPC::ORI), InDSCR) 440 .addReg(InDSCR) 441 .addImm(DSCRValue & 0xFFFF); 442 BuildMI(MBB, IP, dl, TII->get(PPC::MTUDSCR)) 443 .addReg(InDSCR, RegState::Kill); 444 } else 445 errs() << "Warning: Ran out of registers - Unable to set DSCR as " 446 "requested"; 447 } 448 449 if (skipFunction(MF.getFunction()) || !RunPreEmitPeephole) { 450 // Remove UNENCODED_NOP even when this pass is disabled. 451 // This needs to be done unconditionally so we don't emit zeros 452 // in the instruction stream. 453 SmallVector<MachineInstr *, 4> InstrsToErase; 454 for (MachineBasicBlock &MBB : MF) 455 for (MachineInstr &MI : MBB) 456 if (MI.getOpcode() == PPC::UNENCODED_NOP) 457 InstrsToErase.push_back(&MI); 458 for (MachineInstr *MI : InstrsToErase) 459 MI->eraseFromParent(); 460 return false; 461 } 462 bool Changed = false; 463 const PPCInstrInfo *TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo(); 464 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 465 SmallVector<MachineInstr *, 4> InstrsToErase; 466 for (MachineBasicBlock &MBB : MF) { 467 Changed |= removeRedundantLIs(MBB, TRI); 468 Changed |= addLinkerOpt(MBB, TRI); 469 Changed |= removeAccPrimeUnprime(MBB); 470 for (MachineInstr &MI : MBB) { 471 unsigned Opc = MI.getOpcode(); 472 if (Opc == PPC::UNENCODED_NOP) { 473 InstrsToErase.push_back(&MI); 474 continue; 475 } 476 // Detect self copies - these can result from running AADB. 477 if (PPCInstrInfo::isSameClassPhysRegCopy(Opc)) { 478 const MCInstrDesc &MCID = TII->get(Opc); 479 if (MCID.getNumOperands() == 3 && 480 MI.getOperand(0).getReg() == MI.getOperand(1).getReg() && 481 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) { 482 NumberOfSelfCopies++; 483 LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: "); 484 LLVM_DEBUG(MI.dump()); 485 InstrsToErase.push_back(&MI); 486 continue; 487 } 488 else if (MCID.getNumOperands() == 2 && 489 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) { 490 NumberOfSelfCopies++; 491 LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: "); 492 LLVM_DEBUG(MI.dump()); 493 InstrsToErase.push_back(&MI); 494 continue; 495 } 496 } 497 MachineInstr *DefMIToErase = nullptr; 498 if (TII->convertToImmediateForm(MI, &DefMIToErase)) { 499 Changed = true; 500 NumRRConvertedInPreEmit++; 501 LLVM_DEBUG(dbgs() << "Converted instruction to imm form: "); 502 LLVM_DEBUG(MI.dump()); 503 if (DefMIToErase) { 504 InstrsToErase.push_back(DefMIToErase); 505 } 506 } 507 if (TII->foldFrameOffset(MI)) { 508 Changed = true; 509 NumFrameOffFoldInPreEmit++; 510 LLVM_DEBUG(dbgs() << "Frame offset folding by using index form: "); 511 LLVM_DEBUG(MI.dump()); 512 } 513 if (TII->optimizeCmpPostRA(MI)) { 514 Changed = true; 515 NumCmpsInPreEmit++; 516 LLVM_DEBUG(dbgs() << "Optimize compare by using record form: "); 517 LLVM_DEBUG(MI.dump()); 518 InstrsToErase.push_back(&MI); 519 } 520 } 521 522 // Eliminate conditional branch based on a constant CR bit by 523 // CRSET or CRUNSET. We eliminate the conditional branch or 524 // convert it into an unconditional branch. Also, if the CR bit 525 // is not used by other instructions, we eliminate CRSET as well. 526 auto I = MBB.getFirstInstrTerminator(); 527 if (I == MBB.instr_end()) 528 continue; 529 MachineInstr *Br = &*I; 530 if (Br->getOpcode() != PPC::BC && Br->getOpcode() != PPC::BCn) 531 continue; 532 MachineInstr *CRSetMI = nullptr; 533 Register CRBit = Br->getOperand(0).getReg(); 534 unsigned CRReg = getCRFromCRBit(CRBit); 535 bool SeenUse = false; 536 MachineBasicBlock::reverse_iterator It = Br, Er = MBB.rend(); 537 for (It++; It != Er; It++) { 538 if (It->modifiesRegister(CRBit, TRI)) { 539 if ((It->getOpcode() == PPC::CRUNSET || 540 It->getOpcode() == PPC::CRSET) && 541 It->getOperand(0).getReg() == CRBit) 542 CRSetMI = &*It; 543 break; 544 } 545 if (It->readsRegister(CRBit, TRI)) 546 SeenUse = true; 547 } 548 if (!CRSetMI) continue; 549 550 unsigned CRSetOp = CRSetMI->getOpcode(); 551 if ((Br->getOpcode() == PPC::BCn && CRSetOp == PPC::CRSET) || 552 (Br->getOpcode() == PPC::BC && CRSetOp == PPC::CRUNSET)) { 553 // Remove this branch since it cannot be taken. 554 InstrsToErase.push_back(Br); 555 MBB.removeSuccessor(Br->getOperand(1).getMBB()); 556 } 557 else { 558 // This conditional branch is always taken. So, remove all branches 559 // and insert an unconditional branch to the destination of this. 560 MachineBasicBlock::iterator It = Br, Er = MBB.end(); 561 for (; It != Er; It++) { 562 if (It->isDebugInstr()) continue; 563 assert(It->isTerminator() && "Non-terminator after a terminator"); 564 InstrsToErase.push_back(&*It); 565 } 566 if (!MBB.isLayoutSuccessor(Br->getOperand(1).getMBB())) { 567 ArrayRef<MachineOperand> NoCond; 568 TII->insertBranch(MBB, Br->getOperand(1).getMBB(), nullptr, 569 NoCond, Br->getDebugLoc()); 570 } 571 for (auto &Succ : MBB.successors()) 572 if (Succ != Br->getOperand(1).getMBB()) { 573 MBB.removeSuccessor(Succ); 574 break; 575 } 576 } 577 578 // If the CRBit is not used by another instruction, we can eliminate 579 // CRSET/CRUNSET instruction. 580 if (!SeenUse) { 581 // We need to check use of the CRBit in successors. 582 for (auto &SuccMBB : MBB.successors()) 583 if (SuccMBB->isLiveIn(CRBit) || SuccMBB->isLiveIn(CRReg)) { 584 SeenUse = true; 585 break; 586 } 587 if (!SeenUse) 588 InstrsToErase.push_back(CRSetMI); 589 } 590 } 591 for (MachineInstr *MI : InstrsToErase) { 592 LLVM_DEBUG(dbgs() << "PPC pre-emit peephole: erasing instruction: "); 593 LLVM_DEBUG(MI->dump()); 594 MI->eraseFromParent(); 595 NumRemovedInPreEmit++; 596 } 597 return Changed; 598 } 599 }; 600 } 601 602 INITIALIZE_PASS(PPCPreEmitPeephole, DEBUG_TYPE, "PowerPC Pre-Emit Peephole", 603 false, false) 604 char PPCPreEmitPeephole::ID = 0; 605 606 FunctionPass *llvm::createPPCPreEmitPeepholePass() { 607 return new PPCPreEmitPeephole(); 608 } 609