10b57cec5SDimitry Andric //===- PPCMachineScheduler.h - Custom PowerPC MI scheduler --*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // Custom PowerPC MI scheduler. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include "llvm/CodeGen/MachineScheduler.h" 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric namespace llvm { 190b57cec5SDimitry Andric 200b57cec5SDimitry Andric /// A MachineSchedStrategy implementation for PowerPC pre RA scheduling. 210b57cec5SDimitry Andric class PPCPreRASchedStrategy : public GenericScheduler { 220b57cec5SDimitry Andric public: PPCPreRASchedStrategy(const MachineSchedContext * C)230b57cec5SDimitry Andric PPCPreRASchedStrategy(const MachineSchedContext *C) : 240b57cec5SDimitry Andric GenericScheduler(C) {} 250b57cec5SDimitry Andric protected: 26*fe6060f1SDimitry Andric bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, 270b57cec5SDimitry Andric SchedBoundary *Zone) const override; 28*fe6060f1SDimitry Andric 290b57cec5SDimitry Andric private: 300b57cec5SDimitry Andric bool biasAddiLoadCandidate(SchedCandidate &Cand, 310b57cec5SDimitry Andric SchedCandidate &TryCand, 320b57cec5SDimitry Andric SchedBoundary &Zone) const; 330b57cec5SDimitry Andric }; 340b57cec5SDimitry Andric 350b57cec5SDimitry Andric /// A MachineSchedStrategy implementation for PowerPC post RA scheduling. 360b57cec5SDimitry Andric class PPCPostRASchedStrategy : public PostGenericScheduler { 370b57cec5SDimitry Andric public: PPCPostRASchedStrategy(const MachineSchedContext * C)380b57cec5SDimitry Andric PPCPostRASchedStrategy(const MachineSchedContext *C) : 390b57cec5SDimitry Andric PostGenericScheduler(C) {} 400b57cec5SDimitry Andric 410b57cec5SDimitry Andric protected: 420b57cec5SDimitry Andric void initialize(ScheduleDAGMI *Dag) override; 430b57cec5SDimitry Andric SUnit *pickNode(bool &IsTopNode) override; 440b57cec5SDimitry Andric void enterMBB(MachineBasicBlock *MBB) override; 450b57cec5SDimitry Andric void leaveMBB() override; 465ffd83dbSDimitry Andric 47*fe6060f1SDimitry Andric bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) override; 485ffd83dbSDimitry Andric bool biasAddiCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) const; 490b57cec5SDimitry Andric }; 500b57cec5SDimitry Andric 510b57cec5SDimitry Andric } // end namespace llvm 520b57cec5SDimitry Andric 530b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H 54